(in lingua inglese)

Diverse tipologie di ADC a risparmio di potenza sono inizialmente investigate e il modello SAR è infine scelto, in quanto dimostra di essere la soluzione ottimale per l'applicazione studiata. La scelta di utilizzare il multiplexing dei canali di lettura per la conversione analogico-digitale è quindi presentata assieme alle specifiche dell'ADC. La progettazione di ogni componente elettronico del convertitore è poi descritta, iniziando dall'array a capacità commutate che è usato sia come sample and hold, sia come convertitore digitale-analogico. Le dimensioni degli interruttori che forniscono i segnali al DAC sono ottimizzate considerando le specifiche del tempo di assestamento. Una soluzione a basso consumo di potenza è proposta per il comparatore e un registro ad approssimazioni successive è usato per generare i segnali digitali di controllo.

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Politecnico di Milano Scuola di Ingegneria dell''Informazione Corso di Laurea Magistrale in Ingegneria Elettronica Low-Power and Compact Successive Approximation ADC for Bio-Electronic Chips Relatore: Prof. Marco SAMPIETRO Correlatore: Prof. Andreas HIERLEMANN Tesi di Laurea di: Andrea BONETTI matricola 750696 Anno Accademico: 2010-2011 Acknowledgments First of all, I would like to thank my supervisor Prof. Marco Sampietro of

Politecnico di Milano for his continuous support and for making my stay

at ETH Z¨ urich. I am particularly grateful to Prof. Andreas Hierlemann who gave me the unique opportunity to carry out my Master''s Thesis at his

laboratory. Dr. Yihui Chen deserves special thanks for his intelligent guid-

ance through the world of the analog-to-digital converters. I also would like

to express my gratitude to Pascal Meinerzhagen for his helpful suggestions

and to Vijay Viswam for his insightful comments during the completion of

the project. I was truly fortunate to have the possibility to work at the Bio

Engineering Laboratory (BEL) and I owe sincere thanks to all the people I

worked with. 3 Contents 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 MEA Chips Developed at BEL . . . . . . . . . . . . . . . . . 1 1.2.1 Interfacing Electrogenetic Cells in Vitro with CMOS

Microelectrode Arrays . . . . . . . . . . . . . . . . . . 1 1.2.2 The High-Density MEA Chip . . . . . . . . . . . . . . 3 1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . 5 2 Specifications and ADC Topologies 6 2.1 Required ADC for the New Version of the Chip . . . . . . . . 6 2.2 Elaboration of Specifications . . . . . . . . . . . . . . . . . . 6 2.3 Low Power ADC Topologies Overview . . . . . . . . . . . . . 7 2.4 Fully Differential Switched-Capacitor SAR ADC . . . . . . . 10 3 Design implementation 13 3.1 Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Switched-Capacitor Array . . . . . . . . . . . . . . . . . . . . 13 3.2.1 Capacitive Array Design . . . . . . . . . . . . . . . . . 17 3.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.1 Switch Structures . . . . . . . . . . . . . . . . . . . . . 27 3.3.2 DAC Settling Time . . . . . . . . . . . . . . . . . . . . 30 3.3.3 Other Switches . . . . . . . . . . . . . . . . . . . . . . 34 3.4 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.2 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.3 Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . 39 3.5 SAR Control Logic . . . . . . . . . . . . . . . . . . . . . . . . 50 3.5.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . 50 3.5.2 SAR Control Logic Implementation . . . . . . . . . . 53 3.5.3 Delay Elements . . . . . . . . . . . . . . . . . . . . . . 54 3.6 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 4 Simulations and Conclusions 58 4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5 Appendix 64 5.1 Effects of the parasitic capacitances in the DAC . . . . . . . . 64 5.2 Standard deviation estimation of the DAC output voltage . . 65 Bibliography 68 5 List of Figures 1.1 Packaged MEA chip on a custom-designed printed circuit board. 2 1.2 (a) Schematic of a cell attached to a sensor surface. (b) Mi-

crograph of an acute cerebellar brain slice (parasagittal cut)

placed on a CMOS high-density electrode chip for measure-

ments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Micrograph of the MEA chip (7.5 ' 6.1 mm2). . . . . . . . . 3 1.4 Block diagram of the MEA chip. . . . . . . . . . . . . . . . . 4 2.1 Single-slope ADC [4]. . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Successive-approximation ADC structure [4] and a 4-bit analog-

to-digital conversion. . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 First-order sigma-delta ADC [4] . . . . . . . . . . . . . . . . . 9 2.4 3-bit single-ended switched-capacitor SAR ADC. . . . . . . . 10 2.5 4-bit fully differential switched-capacitor SAR ADC. . . . . . 11 2.6 Voltages at VipA and VinA during the sampling and conversion

phases for the 4-bit fully differential switched-capacitor SAR

ADC [8]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Binary weighted switched-capacitor array. . . . . . . . . . . . 15 3.2 Binary weighted switched-capacitor array equivalent circuit. . 16 3.3 2bw1Cs capacitive array. . . . . . . . . . . . . . . . . . . . . . 16 3.4 5bw4Cs capacitive array. . . . . . . . . . . . . . . . . . . . . . 16 3.5 C2C capacitive array. . . . . . . . . . . . . . . . . . . . . . . 16 3.6 2bw1Cs switched-capacitor array with the bottom-plate par-

asitic capacitance added. . . . . . . . . . . . . . . . . . . . . . 18 3.7 2bw1Cs switched-capacitor array equivalent circuit. . . . . . . 19 3.8 INL graph estimation of each split capacitive array. . . . . . . 20 3.9 Modified split capacitive array. . . . . . . . . . . . . . . . . . 23 3.10 Modified split capacitive array equivalent circuit. . . . . . . . 23 3.11 Floorplan of the capacitive array. . . . . . . . . . . . . . . . . 25 3.12 INL graphs of the 9-bit DAC comparing two different values for the unit capacitance. . . . . . . . . . . . . . . . . . . . . . 25 3.13 Capacitive array with ideal bottom-plate and top-plate switches. 28

3.14 Mux-like structure for the switches of the capacitive array. . . 29 6 3.15 Shared-block structure for the switches of the capacitive array. 29

3.16 Dependance of the on-resistance value of the transmission- gate on the input voltage value. While maintaing the rela-

tion (3.26), the value of WN has been swept from 0.7 µm to

7 µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.17 Equivalent RC model of the 9-bit DAC for DIN = 256. . . . . 32 3.18 Simplified equivalent RC model of the 9-bit DAC for DIN = 256. 32

3.19 First-order equivalent RC model of the 9-bit DAC for DIN = 256. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.20 Structure of the comparator stage. . . . . . . . . . . . . . . . 35 3.21 Dynamic latch. . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22 Output response of the latch for a differential sinusoid input signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.23 Load of the dynamic latch. . . . . . . . . . . . . . . . . . . . 37 3.24 Output response of the latch during the regeneration phase.. 38 3.25 Test bench for the input-referred offset voltage estimation of the latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.26 Two-stage preamplifier. . . . . . . . . . . . . . . . . . . . . . 41 3.27 Kickback noise in the first stage of the preamplifier. . . . . . 41 3.28 First preamplifier stage with dummy transistors using the capacitive neutralization technique. . . . . . . . . . . . . . . . 42 3.29 Closed-loop operation of the preamplifier performing the in- put offset storage. . . . . . . . . . . . . . . . . . . . . . . . . 44 3.30 Simplified equivalent circuit of the analog part of the ADC. . 45 3.31 Sampling timing diagram example. . . . . . . . . . . . . . . . 45 3.32 Magnitude and phase diagrams of the open-loop preamplifier transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.33 Step responses of the preamplifier stages for a LSBd''e differ- ential input. The blue trace represents the differential output

voltage of the first stage, while the red trace shows the differ-

ential output voltage of the second stage. . . . . . . . . . . . 48 3.34 Magnitude and phase diagrams of the loop gain transfer func- tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.35 Timing diagrams of the SAR control logic. . . . . . . . . . . . 52 3.36 Timing diagrams for the first three cycles of a conversion. . . 53 3.37 Timing diagrams of the cycles used to determine the last 9 bits of the digital output. . . . . . . . . . . . . . . . . . . . . 54 3.38 Successive approximation register for binary search. . . . . . 55 3.39 Chain of inverters to generate the delayed clock signal. . . . . 55 3.40 Floorplan of the SAR ADC. . . . . . . . . . . . . . . . . . . . 56 3.41 Analog and digital blocks composing the SAR ADC. . . . . . 57 3.42 Layout of the shared digital logic among all the ADCs on chip. 57

3.43 Floorplan of the ADCs integrated on the MEA chip. . . . . . 57 7 4.1 Example of an analog-to-digital conversion performed by the

SAR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 DNL histogram plot of the SAR ADC. . . . . . . . . . . . . . 59 4.3 INL histogram plot of the SAR ADC. . . . . . . . . . . . . . 60 4.4 2''048-points FFT output of the SAR ADC. . . . . . . . . . . 60 5.1 Switched-capacitor DAC equivalent circuit. . . . . . . . . . . 64 5.2 3-bit switched-capacitor DAC and its equivalent circuit. . . . 66 8 List of Tables 1.1 Performance summary of the MEA chip presented in [1]. The

reported values are based on experimental measurements. . . 5 2.1 Specifications for a single ADC. . . . . . . . . . . . . . . . . . 7 3.1 Summary of the most relevant parameters for the available

types of capacitors. . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Examples of the resulting parametric estimation of '(VM,D IN =256) for the bw and 2bw1Cs capacitive arrays. . . . . . . . . . . . 21 3.3 Summary of the results for the design of the capacitive array. 22 3.4 Calculated and simulated settling time for DIN transiting

from 0 to 256. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5 Preamplifier specifications. . . . . . . . . . . . . . . . . . . . . 47 4.1 Summary of the ADC power consumption. . . . . . . . . . . . 60 4.2 Requirements and estimated performance of a single SAR ADC. 61 4.3 Specifications of the single-slope data-conversion system cur-

rently implemented on chip, compared to the performance of

the SAR ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9 Abstract For both the electrical stimulation and recording of cultured neurons, the

CMOS-based microelectrode arrays (MEAs) are one of the most promising

electronic devices used nowadays. To ensure a robust transmission of the

information between the chip and external devices, the MEA chip requires

integrated analog-to-digital converters (ADCs). Moreover, the presence of a

large number of read-out channels on chip poses stringent requirements on

both area and power consumption for the design of the ADCs. Thus, this

Master''s thesis work proposes a low-power and compact successive approx-

imation register (SAR) ADC for such bio-electronic chips. In this thesis, some low-power ADC topologies are first investigated and the SAR ADC is finally chosen, that is the optimum solution for the ap-

plication. The choice of multiplexing the read-out channels of the MEA

chip for the analog-to-digital conversion is then presented while the require-

ments for the ADC are derived. In this work, the design of each part of the

converter is described, starting from the switched-capacitor array which is

usually used as a sample and hold (S/H) as well as a digital-to-analog con-

verter (DAC). The size of the switches that are providing the signals to the

DAC is optimized considering the timing requirements. Furthermore, low

power solutions are proposed for the comparator while good performances

are achieved for both noise and speed. A successive approximation register

logic is finally used to provide the digital control signals. The performance of the SAR ADC is evaluated with post-layout simula- tions. All the preliminary requirements are met and the proposed converter

represents a promising solution for low-power applications. In conclusion,

the specifications of the entire data-conversion system are compared with

the ADCs currently implemented on the MEA device and a possible im-

provement of the chip is presented. Key words: Microelectrode Array (MEA), Switched-Capacitor (SC) Suc-

cessive Approximation Register (SAR) Analog-to-Digital Converter (ADC),

Low-Power, Split Capacitor Array, Offset Cancellation. 10 Sommario Fra i dispositivi che permettono la stimolazione e la misura dell''attivit` a elettrica di colture neuronali, i CMOS microelectrode array (MEA) sono

una delle migliori soluzioni utilizzate oggigiorno. Per una sicura trasmissione

di informazioni dal chip ai dispositivi esterni, il dispositivo MEA richiede

convertitori analogico-digitali (ADC) da integrare nel chip. In particolare,

la progettazione di tali circuiti deve essere eseguita limitando il consumo di

area e potenza in quanto il numero di canali di lettura integrati ` e elevato. Per questo motivo, la presente tesi propone un ADC ad approssimazioni

successive (SAR) compatto e a basso consumo di potenza per chip bio-

elettronici. In questa tesi, diverse tipologie di ADC a risparmio di potenza sono in- izialmente investigate e il modello SAR ` e infine scelto, in quanto dimostra di essere la soluzione ottimale per l''applicazione studiata. La scelta di utilizzare

il multiplexing dei canali di lettura per la conversione analogico-digitale ` e quindi presentata assieme alle specifiche dell''ADC. La progettazione di ogni

componente elettronico del convertitore ` e poi descritta, iniziando dall''array a capacit` a commutate che ` e usato sia come sample and hold (S/H), sia come convertitore digitale-analogico (DAC). Le dimensioni degli interruttori che

forniscono i segnali al DAC sono ottimizzate considerando le specifiche del

tempo di assestamento. Una soluzione a basso consumo di potenza ` e pro- posta per il comparatore e un registro ad approssimazioni successive ` e usato per generare i segnali digitali di controllo. Le prestazioni dell''ADC SAR sono valutate con simulazioni post-layout. Tutte le specifiche stabilite sono soddisfatte e il convertitore proposto rap-

presenta una promettente soluzione per applicazioni a basso consumo di

potenza. La performance dell''intero sistema di ADC integrabile nel dispos-

itivo MEA ` e dunque confrontata con quella degli ADC a singola rampa al momento implementati sul chip e un possibile miglioramento del dispositivo ` e presentato. Parole chiave: Microelectrode Array (MEA), Convertitore Analogico-Digitale

(ADC) ad Approssimazioni Successive (SAR) a Capacit` a Commutate (SC), Basso Consumo di Potenza, Array a Capacit` a Commutate, Cancellazione dell''Offset. 11 Chapter 1 Introduction 1.1 Motivation The CMOS-based microelectrode arrays (MEAs) [1] are sophisticated de-

vices, which can be used to bidirectionally communicate with cultured neu-

rons. They can perform measurements at a high spatial and temporal resolu-

tion, which is hardly achievable with passive MEAs. A switch-matrix-based

high-density MEA chip [2] has been developed at Bio Engineering Labora-

tory of ETH Z¨ urich. With the switch-matrix scheme, an arbitrary subset of around 11''000 electrodes can be selected for recording and stimulation.

By placing the front-end amplifiers outside the array, a high signal-to-noise

ratio (SNR) has been achieved together with a subcellular spatial resolution. To ensure robust and stable transmissions of the information between the chip and other devices on the printed circuit board (Figure 1.1), the

amplified and filtered neural signals are usually digitized by on-chip analog-

to-digital converters (ADCs). The number of neural signals which can be

recorded simultaneously is limited by the number of read-out channels in-

tegrated on the chip, hence, in order to observe the electrical activity of a

large scale neural network, the 126 read-out channels of the previous design

are not sufficient. Therefore, the new version of the chip integrates much

more channels, posing stringent area and power consumption constraints on

the individual read-out channel and ADC. 1.2 MEA Chips Developed at BEL 1.2.1 Interfacing Electrogenetic Cells in Vitro with CMOS

Microelectrode Arrays Complementary semiconductor-metal-oxide (CMOS) technology is a very

powerful technology used to realize substrate-integrated microelectrode ar-

rays. These devices are arrangements of electrodes that can be more or 1 Figure 1.1: Packaged MEA chip on a custom-designed printed circuit board. less directly interfaced to electrogenetic cells, like heart or brain cells. It is

therefore possible to study fundamentals of learning processes and assess the

behavior of electrogenetic cells in vitro by culturing or placing them directly

atop the electronic chips, as shown in Figure 1.2. Figure 1.2: (a) Schematic of a cell attached to a sensor surface. (b) Micrograph of

an acute cerebellar brain slice (parasagittal cut) placed on a CMOS high-density electrode chip for measurements. The CMOS technology plays an important role for such devices since it allows the possibility to address a large number of microelectrodes on the

same chip, leading to a spatial sub-cellular resolution. Another advantage

of using CMOS integrated circuits (ICs) is the high signal quality provided

and the relative low-noise electrophysiological recordings that can be per-

formed from a variety of biological preparations. Many functions can be

programmed via software and digital interfaces. The recording technique is

extracellular and noninvasive, enabling long-term measurements. Applications areas for such devices include neuroscience as well as med- ical diagnostics and pharmacology. The most common biological prepara-

tions studied using microelectrode arrays are acute tissue preparations (e.g,

slices) which are recorded from immediately after they have been cut from 2 the animal and cell cultures. 1.2.2 The High-Density MEA Chip The Bio Engineering Laboratory (BEL) of ETH Z¨ urich designed a CMOS- based microelectrode array [1] featuring 11''011 metal electrodes and 126

read-out channels for extracellular bidirectional communication with elec-

trogenetic cells. The micrograph of the chip is shown in Figure 1.3. The

most important features include: ' High spatial resolution at (sub)cellular level with 3''150 electrodes per mm2. The electrode diameter is 7 µm and the electrode pitch is 18 µm. ' A reconfigurable routing of the recording sites to the 126 read-out channels. ' A low front-end input referred noise of 2.4 µVrms. Figure 1.3: Micrograph of the MEA chip (7.5 ' 6.1 mm2). The high-density arrays are usually CMOS-based devices that over- come the connectivity limitation by making use of on-chip signal multi-

plexing. The simultaneous recording from all electrodes requires the front-

end amplifiers being placed in each pixel (recording site), which, due to 3 area constraints, entails rather high noise levels. Instead of scanning the

entire electrode array, the approach of this device provides a reconfigurable

electrode/readout-channel routing to select an arbitrary subset of electrodes

for recording and stimulation. This enables both, low-noise signal record-

ing, and cellular or subcellular resolution, since the front-end circuitry can

be placed outside the array. Figure 1.4: Block diagram of the MEA chip. In the MEA chip designed by BEL [2] the read-out 126 channels and the associated signal amplification and stimulation circuitry are located outside

the reconfigurable electrode array, where sufficient area for a low-noise circuit

implementation is available (Figure 1.3). The readout channels includes two

amplification and filter stages. Both stages feature digitally configurable

gain and filter settings. The first stage provides bandpass filtering (BPF)

and a gain of 30 dB. The second stage provides an additional gain of either

0 dB, 20 dB or 30 dB with a second LPF. Eight channels are then multiplexed

and buffered by a third stage with an additional gain of 0 dB, 6 dB, 14 dB

or 20 dB, and finally digitized at 20 kHz using successive-approximation

analog-to-digital converters (ADCs) with a resolution of 8-bit. The digital

recording controller then transfers the data off chip by means of a 9-bit bus

together with chip-status information and a CRC (cyclic redundancy check)

for error detection. The chip was fabricated in an industrial 0.6 µm 3-metal 2-polysilicon CMOS-process. The total area of the device is 7.5 ' 6.1 mm2, while the

electrode array covers an area of 2.0 ' 1.75 mm2. The front-end input-

referred noise within the band of 1 Hz to 100 KHz is 2.4 µVrms. The maxi-

mum gain of the entire read-out circuit is 80 dB. The power consumption of

the front-end (first and second stage) is 160 µW/channel while the overall

power consumption of the chip is 135 mW. The most relevant specifications

characterizing the chip are summarized in Table 1.1. 4 Parameter Value Technology 0.6µm 3M2P CMOS Area 7.5 ' 6.1 mm2 Supply voltage analog 5.0 V Supply voltage digital 3.0 V Clock frequency recording controller 3.2 MHz Clock frequency comand controller 8 MHz Number of electrodes 11''011 Sensor area 2.0 ' 1.75 mm2 Electrode density 3''150 1/mm2 Power consumption overall 135 mW Power consumption front-end (stage 1&2) 160 µW/channel Front-end input-referred noise (1 Hz to 100 kHz) 2.4 µVrms Amplification 0-80 dB (18 steps) Table 1.1: Performance summary of the MEA chip presented in [1]. The reported values are based on experimental measurements. 1.3 Thesis Organization Requirements and specifications of the ADC for the new version of the MEA

chip are defined in Chapter 2 where different topologies of converters are an-

alyzed. Chapter 3 presents the design of the SAR ADC, showing the analysis

and simulations of the switched-capacitor array, switches, comparator and

SAR control logic. The characterization of the converter is shown in Chap-

ter 4 where the conclusions are reported. Finally, Chapter 5 is reserved for

the appendix. 5 Chapter 2 Specifications and ADC

Topologies This chapter provides the key design aspects for the new version of the chip.

The choice of multiplexing the read-out channels for the analog-to-digital

conversion is then presented and the requirements for the ADC are derived.

Finally, some low-power ADC topologies are investigated and the optimum

solution for our application is chosen. 2.1 Required ADC for the New Version of the

Chip The presence of on-chip ADCs is an essential requirement for allowing a

robust signal transmission between the chip and the printed-circuit board

(PCB). For the MEA chip presented in [2], 16 successive approximation

ADCs with a 8-bit resolution have been employed. In order to observe the electrical activity of a large-scale neural network, the new version of the chip needs to provide an increased number of channels

NChannels equal to 1''024, which poses stringent area and power consumption

constraints on the individual read-out channel and ADC. In order to improve

the signal quality, in the new design, the number of bits is increased to 10.

For this reason, a thorough noise and offset analyses of the converter are

key aspects that have to be considered during the design. 2.2 Elaboration of Specifications The frequency band for typical neural signals is roughly 10 Hz ' 5 KHz [3].

In order to avoid aliasing and ease spike sorting, the sampling frequency for

a single read-out channel is set to 20 KHz. The number of ADCs is reduced

by multiplexing the signals before their effective conversion. For the new 6 design, a number of 16 ADCs has been aimed to be integrated on the chip,

leading to the following sampling frequency fS for each converter: fS = NChannels NADCs fN = 1024 16 ' 20kHz = 1.28 M S/s (2.1) Due to limited chip area, the area for each ADC is restricted to 1 mm2. To reduce quantization error, 10-bit resolution is chosen while the signal-

to-noise and distortion ratio (SNDR) is set to be larger than 56 dB, which

corresponds to an effective number of bits (ENOB) equal to 9. The new

version of the chip will be designed using a 0.35 µm CMOS technology and

a 3.3 V power supply, aiming to a maximum power consumption of 1 mW

for each ADC. The preliminary specifications are summarized in Table 2.1. Parameter Value Resolution 10 bits Sampling rate 1.28 MS/s SNDR ' 56 dB Power consumption ' 1 mW Supply voltage 3.3 V Technology 0.35 µm CMOS Area ' 1 mm2 Table 2.1: Specifications for a single ADC. 2.3 Low Power ADC Topologies Overview In order to evaluate to evaluate which ADC architecture [4] best satisfies the

presented requirements, some of the most important topologies are briefly

reviewed in this section. Integrating ADC The Integrating ADC can be an appropriate solution for low-speed appli-

cations where low power consumptions are required. A possible implemen-

tation of this topology is the single-slope architecture, shown in Figure 2.1,

where the input signal is compared with a voltage ramp. Counting the time

required by the ramp to reach the signal value, it is possible to perform

the analog-to-digital conversion. Even if this solution presents a very sim-

ple structure (a comparator, the voltage ramp generator and the counter

in principle), it suffers from several drawbacks. A stable and precise ramp

generator is required since voltage and temperature coefficients can affect 7 the linearity of the conversion. Moreover, a high clock frequency is desired

in order to reach a sufficient resolution. Figure 2.1: Single-slope ADC [4]. Successive-Approximation ADC The successive-approximation ADC is based on the binary search algorithm

and it requires a simple structure based on a sample and hold (S/H), com-

parator, digital-to-analog converter (DAC) and the successive approxima-

tion register (SAR). This is a topology mostly used to design medium-high

resolution ADCs for medium-low speed applications. The DAC is controlled

by the SAR logic and its output voltage varies depending on the decision of

the comparator, as shown in Figure 2.2. Besides the simple structure, the

converter presents a low power consumption as well. Sigma-Delta ADC The Sigma-Delta ADC is one of the best solutions if high resolution is re-

quired in low frequency applications. The converter is based on the oversam-

pling and noise shaping techniques and it can achieve high signal-to-noise

ratio (SNR). The analog part of the circuit is simple since only a compara-

tor, voltage reference, integrators and analog summing circuits are required.

On the other hand, the digital circuitry is quite complex and it consists of

a digital signal processor (DSP) which acts as a digital filter and decimator

(Figure 2.3). The delta modulation is used to achieve higher transmission

efficiency by transmitting the changes (delta) in value between consecutive

samples. Combining the oversampling with the sigma-delta modulator it 8 Figure 2.2: Successive-approximation ADC structure [4] and a 4-bit analog-to- digital conversion. is possible to obtain a high SNR at low frequencies by shaping the quanti-

zation noise such that most of it occurs outside the bandwidth of interest.

The noise outside the frequency bandwidth of interest will be removed by

the digital filter while the decimator will reduce the output data rate back

to the Nyquist rate. Some of the disadvantages of this structure are the high

clock frequency required and the large silicon area consumed by the digital

part. Figure 2.3: First-order sigma-delta ADC [4] 9 2.4 Fully Differential Switched-Capacitor SAR ADC Considering the ADC specifications mentioned in Section 2.2, the successive

approximation ADC has been preferred among the three different low-power

ADC topologies presented. The most relevant advantages of this topology

are the following: ' Low power consumption: Since the SAR ADC does not contain any power-hungry operational amplifiers (OpAmps), it is a well-known

topology for its power efficiency. In fact, the comparator usually con-

sumes less than an OpAmp since it does not need linear settling. ' Simple structure: The low complexity of the circuit ease its imple- mentation on chips where compact realizations are required. This is

also due to the very simple principle on which the ADC is based, the

binary search algorithm. Moreover, promising solutions can also be

evaluated in order to reduce even more the total area required by the

ADC. In particular, the converter presented in this work is a fully differen- tial switched-capacitor or charge-redistribution SAR ADC [5]. This circuit

incorporates an array of capacitors that is usually used as a S/H as well

as a DAC. In order to better understand the operation, we first consider a

simple single-ended 3-bit switched-capacitor ADC with a binary weighted

capacitive array [6], which is shown in Figure 2.4. The main parts of the

circuit are: the capacitive array, the switches, the comparator and the SAR

control logic. Figure 2.4: 3-bit single-ended switched-capacitor SAR ADC. During the sampling phase, the top plates of the capacitors are reset to the common voltage VCM while all the bottom plates of the capacitors are

connected to the input signal source Vsig that is equal to the sum of VCM

and the input signal component ''Vsig. The switches resetting the input

node of the comparator are then turned off and all the bottom plate nodes

are connected to VCM , performing the so-called ''bottom plate sampling'' [7].

Now that the voltage VCM '' ''Vsig is stored on the top plate node of the 10 capacitors, the switch controlled by D2 is connected to VREF and a voltage

equal to VREF /2 is added to VCM '' ''Vsig. The comparator can therefore

determine the most significant bit (MSB) by comparing this value with VCM .

The SAR control logic either leaves the switch controlled by D2 connected

to VREF or connects it back to VCM depending on the comparator output.

A similar process is followed for the remaining two bits leading to the deter-

mination of the digital output value. All the switches are then reset again

to the initial positions and the converter can start another cycle of conver-

sion [4]. Note that the extra LSB capacitor (C in the case of the 3-bit DAC)

is required to make the total value of the capacitive array equal to 8C, so

that binary division is accomplished when the individual bit capacitors are

manipulated. Using the same switched-capacitor array of the previous example and considering a fully differential topology of the circuit, the 4-bit ADC shown

in Figure 2.5 is obtained. This new structure differs from the single-ended

one in Figure 2.4 in various aspects, i. e., the differential input signal for

the comparator, two identical capacitive arrays and two different references

voltages VREF P and VREF N . Note that this structure gains an additional bit

D3 that is the ''sign bit'' and it is determined once the differential input signals

are sampled on the input nodes of the comparator. Hence, the MSB bit

corresponds to the sign of the output digital value. Each reference voltage is

assigned to a capacitive array depending on the result of the sign bit decision.

At this point, the switch controlled by D2 in each array is connected to

the respective reference voltage and the values of the remaining 3 bits are

determined using the binary search algorithm, as explained in the single-

ended example. The voltages at the input nodes of the comparator, VipA and

VinA, during the sampling and conversion phases are shown in Figure 2.6. Figure 2.5: 4-bit fully differential switched-capacitor SAR ADC. 11 Figure 2.6: Voltages at VipA and VinA during the sampling and conversion phases for the 4-bit fully differential switched-capacitor SAR ADC [8]. Since the overall accuracy and linearity of the SAR ADC is primarily determined by the internal DAC, the switched-capacitor realizations of it

have become very popular in newer SAR ADCs due to their high accuracy

and linearity. A high degree of temperature stability is another advantage

of these capacitive DACs. Moreover, the fully differential analog signal path has been preferred respect to a single-ended one for the following main

reasons: ' Immunity to common-mode noise. ' The input dynamic range is doubled, which relaxes the design require- ments of the comparator. 12 Chapter 3 Design implementation 3.1 Design Guidelines The design of the SAR ADC has been conducted focusing on the power

and area constraints while maintaining good linearity performances for the

analog-to-digital conversion. Switched-capacitor arrays are used to imple-

ment both the S/H and DAC while minimizing the area of the unit capac-

itor. Parasitic capacitances and matching properties have been taken into

account during the analysis. Switches are providing the signals to the DAC

and their size has been optimized focusing on the timing requirements. A

low power solution is proposed for the comparator while achieving good noise

performances and speed requirements. The input-offset storage technique

has been chosen for this stage and a dynamic latch has been preferred. The

digital control signals are provided by a successive approximation register. 3.2 Switched-Capacitor Array The design of the switched-capacitor array is a key aspect for the overall

performance of the entire SAR ADC. Generally, the array is used as: ' S/H : the differential input voltage can be stored at the input nodes of the comparator using the bottom plate sampling technique [7]. ' DAC : in combination with the SAR control logic, the switched-capacitor array can provide the required voltage variations to perform the binary

search. Usually the capacitive array is the part of the circuit that requires the largest

silicon area due to a large number of capacitors. Different design solutions

can be taken into account to reduce the size of the array while maintaining a

good linearity performance for both S/H and DAC. In particular, the struc-

ture of the array can be modified and the unit capacitor can be minimized. 13 However, these design choices can lead to larger parasitic capacitances and

worse matching. For this reason, an accurate and precise analysis is required

in order to choose the best solution. The analysis should cover also the choice of the type of capacitor. The available technology offered two main types: poly-poly (cpp) capacitors and

metal-metal (cmm) capacitors. The most relevant parameters describing

these topologies in terms of capacitance, bottom plate parasitic capacitance

and matching parameters are summarized in Table 3.1. cpp capacitor cmm capacitor Area capacitance 0.85 fF/µm2 1.25 fF/µm2 Perimeter capacitance 0.021 fF/µm 0.111 fF/µm Parasitic area capacitance 105 aF/µm2 12 aF/µm2 Parasitic perimeter capacitance 57 aF/µm 36 aF/µm Minimum area 17.24 µm2 25 µm2 Minimum unit capacitance 15 fF 33.47 fF Matching parameter AC 1.25% µm 0.65% µm Table 3.1: Summary of the most relevant parameters for the available types of capacitors. The capacitor matching is described by the following equation: ' ''C C = AC '' W L (3.1) where ' ''C C is the standard deviation of the difference ''C of identically designed capacitors, normalized to their absolute value C. The parameters

W and L define the geometric size of the capacitor. Since the MSB is the sign bit, two identical 9-bit capacitive arrays are required for the SAR ADC. Most of the analyses have been conducted con-

sidering only one capacitive array, extending then the results to the differ-

ential case. For this reason, it is better to differentiate the least significant

bit (LSB) definition in the two following cases: ' Differential signal path: the required resolution n of the ADC is 10 bits for a differential dynamic input range of F Sd''e = 4V . The input

signal for the ADC is in fact differential and each single-ended signal

has a range of 2V. This results in a differential LSBd''e equal to: LSBd''e = F Sd''e 2n = 4V 210 '' 3.906 mV (3.2) ' Single-ended signal path: since the switched-capacitor DAC is con- trolled by a 9-bit digital input signal DIN , it is possible to define 14 the single-ended LSBs''e. This value is useful to evaluate the perfor-

mance of each DAC and then estimate the differential performance

while adding linearly this error, which represents the worst case. LSBs''e = VREF P '' VCM 29 = 1V 29 '' 1.953 mV (3.3) Note that, depending on the sign bit, the analog input range of the single-

ended signals becomes either [1.65 , 2.65] V or [0.65 , 1.65] V. However, the

value of the single-ended full scale range F Ss''e is equal to 2 V, as expected. Split Capacitive Array The most popular switched capacitor DAC is an array of parallel binary-

weighted capacitors [6]. The structure is shown in Figure 3.1 for a 9-bit

DAC where the capacitor C is equal to the unit capacitor chosen. After

being discharged, the bottom plates of the capacitors are connected either

to a reference voltage or to VCM , determining an output voltage Vm which

is a function of the voltage division between the capacitors. The equivalent

circuit of the DAC is shown in Figure 3.2. Considering m as the number

of capacitors connected to the reference voltage VREF P , the equation giving

the value of Vm is the following: Vm = VCM + (VREF P '' VCM ) m 29 (3.4) Figure 3.1: Binary weighted switched-capacitor array. As a drawback, the presented capacitive array requires a large area due to the large number of capacitors. The total capacitance of the array is in fact

29C, which can result also in a large dynamic power consumption. A possible

solution that can be considered is splitting the array in parts using one or

more series capacitors [6]. Maintaining the binary weighted capacitor size

for the sub-arrays and choosing the correct values for the series capacitors, it

is possible to maintain the same ratios for the voltage division, obtaining the

identical equation given in (3.4). For the 9-bit switched capacitor DAC, the

array can be split in two parts (2bw1Cs array), five parts (5bw4Cs array) or

it can be even realized with a C-2C ladder (C2C array) [9]. These topologies

are shown in Figures 3.3, 3.4 and 3.5 where the total capacitance is in fact 15 Figure 3.2: Binary weighted switched-capacitor array equivalent circuit. Figure 3.3: 2bw1Cs capacitive array. Figure 3.4: 5bw4Cs capacitive array. Figure 3.5: C2C capacitive array. reduced (e.g., the 2bw1Cs presents a total capacitance of approximately

48.07C).

However, the series capacitors introduce bottom-plate parasitic capacitances

that are affecting the top-plate nodes of the sub-arrays, hence decreasing the

linearity of the ADC. In addition, the matching is also degraded due to the 16 capacitors whose value is a fraction of the unit capacitor, such as 16

15 C and 4

3 C . An accurate analysis of these effects is therefore required in order to choose a split capacitive array that provides the required linearity and

matching for the DAC, while occupies the smallest chip area. 3.2.1 Capacitive Array Design Thermal Noise (kTC Noise) The first limiting factor for the minimum acceptable size of the capacitors

is the Johnson-Nyquist noise (thermal noise) that is usually referred as kTC

noise for the sampling circuits [6]. Considering that the entire ADC has two

capacitive arrays, the mean-square value expressing the thermal noise for

each array is summed up while considering the SNR of the entire structure.

Since the two arrays are identical, the worst SNR due to the kTC noise can

be written as follows: SN RT hermal = PSignal PT hermal = 10log10

1 2 F Sd''e 2 2 2 kBT Cu

(3.5) where kB is the Boltzmann constant, T is the temperature expressed in

Kelvin and Cu is unit capacitor considered. Since for all the different split

capacitive array topologies there is always a unit capacitor connected to the

output node of the DAC, this capacitive value has been considered for the

calculation as worst case. Comparing this SNR with the theoretical signal-

to-quantization-noise-ratio (SNQR) of the ADC, it is possible to find a value

of the capacitor Cu that returns a negligible kTC noise. The definition of

the SQNR is the following: SQN R = 10log10

1 2 F Sd''e 2 2 LSBd''e 12

= 6.02n + 1.76 (3.6) For a 10-bit ADC, the theoretical SQNR is equal to 62 dB. The value of the

unit capacitor is therefore found considering the following condition: SN RT hermal ' SQN R (3.7) That results in the a minimum capacitor values at a temperature T of 300 K

equal to: Cu ' 10 6.02n+1.76 10 ' 4kBT 2 F Sd''e 2 '' 6.55 f F (3.8) Being 15 fF and 33.47 fF respectively the minimum unit capacitance Ccpp,min

and Ccmm,min for the technology considered (Table 3.1), the effect of the kTC

noise is not relevant and it can be neglected in the future considerations. 17 Parasitic Capacitances Every integrated capacitor presents parasitic capacitances between its plates

and the surrounding layers. This parasitics can be therefore summarized in

two groups: top-plate (TP) parasitic capacitances and bottom-plate (BP)

parasitic capacitances, depending on which plate is considered. Since usually

the BP parasitic capacitances presents the highest value, the effect of the

TP parasitic capacitances has been neglected during the presented analysis.

Considering first the bw capacitive array (Figure 3.1), the BP nodes of all

the capacitors are always connected to a fixed voltage value (either to a

reference voltage or VCM ), hence the parasitic capacitances are not affecting

the DAC characteristic of the output voltage. This is not true for the split

arrays where the series capacitors are adding parasitics on the TP nodes of

the sub-arrays, giving a gain error and decreasing the linearity of the DAC.

As an example, the 2bw1Cs capacitive array is shown in Figure 3.6 where

the BP parasitic capacitance Cp1 of the series capacitor Cs1 has been added.

Note that Cp1 is considered to be connected between the top-plate of the

LSB sub-array and the n-well where the capacitive array is placed. This

well is tied to VDD. Figure 3.6: 2bw1Cs switched-capacitor array with the bottom-plate parasitic ca- pacitance added. Both effects can be highlighted in the equation of the output voltage of the

DAC, which is obtained by solving the system of equations given by the

charge conservation principle. Considering the 2bw1Cs capacitive array as

an example, the equivalent circuit of the DAC is shown in Figure 3.7 where

m and p are the sums of the unit capacitors connected in parallel to the

reference voltage in the LSB sub-array (C6''9) and MSB sub-array (C1''5)

respectively. The values of m and p depend on the digital input DIN of the

DAC, for example: if DIN = 256 = 100...0, then m = 0 and p = 16.

Assuming that all the capacitors are discharged before applying the digital

input signal, the equations given by the charge conservation principle are

the following: Cp1(VCM '' VDD) = mC(VL '' VREF P ) + (16 '' m)C(VL '' VCM ) + + 16 15 C(VL '' VM ) + Cp1(VL '' VDD) 18 Figure 3.7: 2bw1Cs switched-capacitor array equivalent circuit. 0 = pC(VM '' VREF P ) + (31 '' p)C(VM '' VCM ) + 16 15 C(VM '' VL) (3.9) Solving the previous system of equations, the output voltage VM of the DAC

is: VM = VCM +(VREF P ''VCM ) 16(m + 16p)C 8192C + 481Cp1 + 15pCp1 8192C + 481Cp1 (3.10) While not considering the parasitic capacitance (Cp1 = 0) the equation is

reduced to the output voltage equation of an ideal 9-bit DAC: VM = VCM + (VREF P '' VCM ) m + 16p 512 (3.11) Comparing (3.10) with (3.11) it is therefore possible to note how the parasitic

capacitance Cp1 is affecting both gain error and linearity. Focusing on the linearity of the DAC, the integral nonlinearity (INL) graph can be estimated for each presented topology. This can be done by solving the equations given by the charge conservation principle while

considering the BP parasitic capacitances, finding the equation of the output

voltage and proceeding then with the INL estimation. The INL values have

been found comparing the effective output voltage with its best fitting line

in order to eliminate the gain error [4]. As an example, the estimated INL

graph for each split capacitive array topology is shown in Figure 3.8 where

minimum-size cmm capacitors have been used. The binary weighted solution

has not been considered since no BP parasitic capacitances are connected

to the TP node of the array. Note that each graph has been found while

considering only one capacitive array, hence the LSB considered is referred

to the single-ended case, that has been estimated in (3.3). The results can

be extended to the differential case since both capacitive arrays in the ADC 19 are identical. From the INL results shown in Figure 3.8, it is possible to

notice that the more the array is divided into parts, the more it is affected

by the parasitic components. Hence, the area of the unit capacitor should

be increased in order to reduce the parasitic capacitances and limit this

effect. The tradeoff between the linearity and required area will be therefore

considered while comparing all the results, aiming the following requirement: IN L ' 0.5LSBs''e (3.12) Figure 3.8: INL graph estimation of each split capacitive array. Matching of the Capacitors The matching of the capacitors is another key aspect that has to be taken

into account in order to achieve a desired performance from the capaci-

tive DAC. The matching properties of capacitors depend on the technology

used, the capacitor size and the layout employed. While for the layout design a common-centroid technique has been considered (Section 3.6), in

this section, a pre-layout estimation of the capacitors matching has been

studied [10]. The output voltage of each 9-bit DAC for the half-range dig-

ital input code (DIN = 256 = 100...0) presents the worst case in terms of

mismatch among the capacitors [11], hence the standard deviation of this

voltage should be constrained with the following condition: 3'(VM,D IN =256) ' 0.5LS Bs''e (3.13) 20 where VM,D IN =256 is the output voltage value for the half-range digital input code and is ideally equal to: VM,D IN =256 = VC M + VREF P '' VCM 2 = 2.15 V (3.14) If (3.13) is satisfied, the linearity performance of the DAC is met. Note that

if the requirement is met considering only one capacitive array, the result

can be extended also for the differential case. Considering the parametric

expression of the output voltage of the DAC and assuming that the mis-

match of each capacitor is independent, it is possible to estimate both the

mean value and the standard deviation of '(VM,D IN =256). The calculations have been conducted using the properties of the variance from the statis-

tics theory. A simplified example of this type of calculation is reported in

Appendix 5.2 for a 3-bit capacitive DAC. This type of estimation has been

conducted for each capacitive array topology presented before. The values of

'(VM,D IN =256) for both the bw and 2bw1Cs capacitive array are presented in Table 3.2, where µC is the mean value of the unit capacitor considering

both area and perimeter capacitance (Table 3.1) and 'C is the standard

deviation of the unit capacitor, that is defined as follows: 'C = ' δC C µC = ' ''C C '' 2 µC (3.15) Capacitive array topology '(VM,D IN =256) bw (VREF P '' VCM ) '' 3'C 32 '' 2µC 2bw1Cs (VREF P '' VCM ) 'C q 24591µ2 C + 15' 2 C 1024µ2 C Table 3.2: Examples of the resulting parametric estimation of '(VM,D IN =256 ) for the bw and 2bw1Cs capacitive arrays. Since both µC and 'C depend on the area of the unit capacitor, by substi-

tuting the parametric expressions in (3.13), one can determine the minimum

unit capacitor area that satisfies the condition. The results found with the

analytical method have been compared with MATLAB simulations where

the '(VM,D IN =256) value has been calculated considering the capacitor vari- ables as 100-points gaussian distributions. The comparison shows that the

proposed method overestimates the minimum unit capacitor area and this is

probably due to the independent-variables assumption. However, this type

of analysis can still be used to roughly determine the unit capacitance with

some margin. 21 Results and Considerations Summarizing all the results found in the previous analyses, one can decide

the capacitive array topology, the type of capacitor and its unit area that

best fit for our application. Since the kTC noise can be considered negligi-

ble, the minimum unit capacitor area W L that satisfies both the parasitic

capacitance (PC) condition (3.12) and the capacitive matching (CM) con-

dition (3.13) are summarized in Table 3.3. PC CM Overall WL [µm2] WL [µm2] WL [µm2] # Cu CT ot [fF] bw cpp min min min 512 7''682 cmm min min min 512 17''137 2bw1Cs cpp 17.28 min 17.28 48.07 722 cmm min min min 48.07 1609 5bw4Cs cpp 140.63 >1''000 >1''000 - - cmm 38.03 105 105 20.50 2''784 C2C cpp 248.27 >1''000 >1''000 - - cmm 74.95 >1''000 >1''000 - - Table 3.3: Summary of the results for the design of the capacitive array. The total number of unit capacitors required in the array is # Cu and CT ot is

the total capacitance of the array. The min value states that the minimum-

size unit capacitor satisfies the considered design condition. On the other

hand, when a unit capacitance area less than 1''000 µm2 cannot satisfy the

matching condition for a certain condition, the topology is discarded. As

expected, it is possible to notice how the split topologies are affected by

both parasitics and mismatch. In particular, the 5bw1Cs and C2C can be

discarded since they require a very large unit capacitor mostly due to the

presence of BP parasitic capacitances. Hence, the 2bw1Cs capacitive array

has been chosen since it meets the requirements with the minimum unit

capacitance value. Furthermore, cmm capacitors have been preferred due

to their better matching characteristic and less parasitic capacitances. Split Capacitive Array Realization The 2bw1Cs capacitive array chosen includes a series capacitor Cs1 with a

value of 16

15 C whose layout design could be cumbersome. In addition, its matching properties could be worse than those of the other capacitors since 22 its capacitance is not an integer multiple of the unit capacitor C. Therefore,

the modified split capacitive array presented in [13] has been adopted in this

work. The modified array, shown in Figure 3.9, differs from the common

2bw1Cs structure for the following two aspects: ' The series capacitor is substituted with a unit capacitor, i. e., Cs1 is equal to C. ' The additional parallel capacitor Ce of the LSB sub-array is removed. Figure 3.9: Modified split capacitive array. In order to check the accuracy of the proposed solution, it is possible to study the equivalent circuit of the DAC, which is shown in Figure 3.10.

Assuming that all the capacitors are discharged before applying the digital

input signal and neglecting the effect of the parasitic capacitance (Cp1 = 0),

the equations given by the charge conservation principle are the following: 0 = mC(VL '' VREF P ) + (15 '' m)C(VL '' VCM ) + C(VL '' VM )

0 = pC(VM '' VREF P ) + (31 '' p)C(VM '' VCM ) + C(VM '' VL) (3.16) Figure 3.10: Modified split capacitive array equivalent circuit. Solving the previous system of equations, the output voltage VM of the DAC

is found as follows: 23 VM = VCM + (VREF P '' VCM ) m + 16p 511 (3.17) Comparing (3.11) with (3.17), it can be noticed that a gain error of 1 LSB

introduced by the proposed array. However, this is not severe since the

gain error caused by the input capacitance of the comparator is even larger

(Appendix 5.1). DAC Post-Layout Simulations on Cadence The reliability of the previous analyses can be verified by simulating the

DAC with Cadence. First of all, the linearity of the DAC is evaluated by

running an INL analysis which, however, takes into account only the effects

of the parasitic capacitances. The results given by the pre-layout simulations

match the previous estimated values. Nevertheless, the performance of the

DAC decreases while checking the post-layout simulations. This is due to

the two following aspects: ' The parameters describing the different capacitor technologies (Ta- ble 3.1) are defined as mean values. The minimum unit capacitance

can be considered as a boundary case, hence the estimations could be

not accurate enough. ' The post-layout simulations take into account the coupling effects be- tween the capacitors and wires, that are difficult to estimate. This

aspect can be critical since the unit capacitance could be comparable

to the parasitic and wiring capacitances. For this reason, the layout design of the capacitive array has been conducted

in order to reduce the parasitic effects and maximize the DAC performance.

The common-centroid technique [15] has been chosen to reduce the com-

plexity of the structure and, hence, minimize the wiring. In addition, while

the metal layers MET2 and MET3 have been reserved for the capacitors

and the internal connections, MET1 has been used to wire the input signals

and to reduce capacitive unbalances of the structure due to the asymmetric

structure. The capacitive array floorplan is shown in Figure 3.11 where Csd

is the dummy capacitor of Cs1.

The modified split capacitive array implemented with minimum unit capac-

itors (Cu=33.47 fF) manifests an INL that is always less than 0.5 LSBs''e.

However, the unit capacitor Cu has been finally increased to 64.36 fF in

order to have some margin on the performance. The INL graphs of both

cases are shown in Figure 3.12. The DAC non-linearity caused by the capacitance mismatch has been verified with a 1''000-runs Monte Carlo simulation. The worst-case value of

VM,D IN =256 has been considered and measured. The following results have been obtained: 24 Figure 3.11: Floorplan of the capacitive array. Figure 3.12: INL graphs of the 9-bit DAC comparing two different values for the unit capacitance. 25 ' µ(VM,D IN =256) = 2.150 V ' '(VM,D IN =256) = 82.30 µV It is possible to compare the standard deviation of VM,D IN =256 with the 0.5 LSBs''e reference value as follows: 3'(VM,D IN =256) = 246.90 µV 0.5 LSBs''e '' 1.953 mV (3.18) Hence, the estimations about the DAC non-linearity are reliable. Dynamic Power Consumption The dynamic power consumed in the array can be estimated considering

both the power required by the DAC and the power delivered during the

sampling phase [14]. Considering only one capacitive array, it is possible to

estimate these values as follows: PDAC = fS 9 X i=1 Ei '' fSCChargedV 2 REF (3.19) PSamp = fSESamp = fSCCharged F Ss''e 2 2 (3.20) where fS is the sampling frequency which is equal to 1.28 MS/s, Ei the

energy required by the DAC for the i-th digital input applied, CCharged is

the total capacitance charged during the DAC phases (note that the voltage

across the series capacitor is assumed to remain the same) and is equal to

46C, VREF is the voltage at which each capacitor is charged and is equal to

1 V and ESamp is the energy required by the sampling phase. Considering

both capacitive arrays, their total dynamic consumption is therefore the

following: PT ot = 2(PDAC + PSamp) '' 2fSCCharged " V 2 REF + F Ss''e 2 2 # (3.21) Which results in a total power consumption PT ot equal to 15.16 µW. Since

the total power required to charge the array is proportional to CCharged, it

is favorable to split the array. For a conventional binary weighted array, the

equivalent charged capacitance is 512C which leads to a PT ot of 168.72 µW

for the same unit capacitance. The previous estimated values can be verified by a simple simulation on Cadence. Considering first the DAC phase, the switching behavior can

be simplified in two steps: while the top-plate nodes of both MSB and

LSB sub-arrays are first maintained at VCM , the bottom-plate nodes of

all capacitors excluding Cs1 are switched between VREF P and VCM . The 26 switching frequency of this circuit has to be equal to 1.28MS/s that is the

sampling frequency fS. Hence, the power consumed by the DAC can be

estimated as follows: PDAC,Sim '' (VREF P '' VCM )IAvg (3.22) where IAvg is the average current delivered by the reference voltage source

calculated on 1''000 cycles. For the sampling phase, the switching behavior

is the same and, instead of VREF P , the maximum input voltage value is

applied. Since this value is theoretically equal to 2.65V, that is actually

VREF P , both the circuit and the conditions are exactly equal to the previous

case. Hence, PSamp,Sim is equal to PDAC,Sim, as obtained also in the previous

calculations. The total dynamic consumption estimated before is verified by

this simulation, as it can be noticed from the results: PT ot,Sim = PDAC,Sim + PSamp,Sim '' 2(VREF P '' VCM )IAvg = 15.59 µW (3.23) 3.3 Switches Each capacitive array requires a relatively high number of switches that are

used both for passing signals and reset the voltage values at specific nodes.

A design analysis based on the settling time and sampling linearity has been

conducted in order to optimize the size of each switch. 3.3.1 Switch Structures The switched-capacitor array is used both for sampling the input signal and

providing comparing reference voltages required by the SAR algorithm. In-

put and reference signals are applied to the bottom-plate of the capacitors

using switches. On the other hand, the top-plates of the capacitors belong-

ing to the LSB sub-array are reset by applying the common-mode voltage

VCM through only one switch (Figure 3.13) while the node VM is reset by

the preamplifier stage during the offset-cancellation phase, as shown in Sec-

tion 3.4. For this reason, the switches used can be divided into two groups: ' Bottom-plate switches: they pass the input voltage signal, the common voltage or one of the two reference voltages to the bottom-plate of the

capacitors. ' Top-plate switch: it resets the voltage value at the VL node passing the common voltage. The structure of the entire capacitive array with the switches is shown in

Figure 3.13 where VBP can be one of the four voltages mentioned before and

here summarized with their voltage values or range: 27 ' 0.65 V ' VSig ' 2.65 V ' VCM = 1.65 V ' VREF P = VCM + VREF = 1.65 V + 1 V = 2.65 V ' VREF N = VCM '' VREF = 1.65 V '' 1 V = 0.65 V Figure 3.13: Capacitive array with ideal bottom-plate and top-plate switches. Starting first the design of the BP switches, they can be organized choos- ing one of the following main structures: ' Mux-like (ML) structure: four different switches are connected to the bottom plate of each capacitor in the array, respectively passing the

voltages VSig, VREF P , VREF N and VCM . Figure 3.14 shows the struc-

ture connected to the bottom plate of one capacitor. ' Shared-block (SB) structure: the bottom plate of each capacitor is di- rectly connected to two switches only. While one switch is passing

VCM , the other is connected to a structure shared among all the ca-

pacitors belonging to the array. This structure is made up of three

switches that are providing the remaining voltages (VSig, VREF P and

VREF N ). This topology is shown in Figure 3.15 where the shared block

has been highlighted. The SB structure has been implemented because it requires a less compli-

cated control logic and routing due to the shared structure. Although the

switches are connected in series, this solution does not need very low switch

on-resistance. Still good performances can be achieved while maintaining

small gate-width and minimum gate-length for all the transistors used. Only NMOS pass-transistors (NMOS PTs) have been used to implement the switches passing the negative reference voltage VREF N and common

voltage VCM while PMOS pass-transistors (PMOS PTs) are used to provide

the highest reference voltage VREF P . On the other hand, transmission-

gates (TGs) are preferred while passing the input voltage, whose range is

from 0.65 V to 2.65 V. Considering the SB structure, the switch T GBP that

controls the passage of VSig, VREF P and VREF N for each capacitor is also a 28 Figure 3.14: Mux-like structure for the switches of the capacitive array. Figure 3.15: Shared-block structure for the switches of the capacitive array. transmission-gate. The on-resistance values of both NMOS PT and PMOS

PT depend on the input signal VSig and their definitions are shown in (3.24)

and (3.25) respectively [12]. Ron,N = 1 µnCox W L N (VDD '' VSig '' VT N ) (3.24) Ron,P = 1 µnCox W L P (VSig '' |VT P |) (3.25) 29 where Cox is the MOS gate capacitance per unit area, W L the aspect ratio and VT the threshold voltage. Since the electron mobility µn of the NMOS

transistors is approximately three times larger than the hole mobility µp of

the PMOS transistors for our technology, a scaled value of the minimum

gate-width can be used while sizing the PMOS switches. Hence, assigning

WP for the gate-width of the PMOS transistor and WN the gate-width of

the NMOS transistor, the relation between them is expressed as follows: WP = 3WN (3.26) Therefore, following the relation given by (3.26) and minimum gate-length

for the design of all the PTs, it is possible to reach a low on-resistance

value for the PMOS PTs that is comparable to the one of the minimum-

size NMOS switches for the respective input voltage ranges. Using the same design choice for the design of the transmission-gates, the variation

of its on-resistance as a function of the input voltage will be much less

compared to that of a pass-transistor. This result is shown in Figure 3.16

where this function has been plotted considering different values for WN

and maintaining the ratio given by (3.26). Finally, as a reference value, the

minimum size and aspect ratio for the gate of the NMOS transistors of the

switches provided by the technology used in this thesis are the following: W L N,min = Wmin Lmin = 0.7 µm 0.35 µm = 2 1 (3.27) 3.3.2 DAC Settling Time Most of the switches has been sized considering the settling time require-

ment of the DAC. During the settling phase, all the BP switches are in-

volved except for the shared transmission-gate that is directly passing the

input signal. It is therefore useful to study the RC equivalent model of

the switched-capacitor array where the switches are represented with their

on-resistance. The settling time of the output voltage provided by the 9-bit DAC reaches its largest value when the digital input is switched from DIN = 0

to DIN = 256, since the voltage difference between the initial and the fi-

nal value presents its maximum value which is ''V '' VREF 2 = 0.5 V . For the digital input value DIN = 256, the bottom plate of the capacitor C1 is

therefore connected to the series of the switches composed by T GBP and

one pass-transistor (NMOS or PMOS depending on the reference voltage)

while the bottom-plate of each other capacitor is connected to VCM through

the NMOS switch. Note, at this moment the TP reset switch is turned off.

The equivalent RC model is shown in Figure 3.17. In order to obtain a rough estimation of the settling time, it is gener- ally common to use the Open Circuit Time Constant (OCTC) analysis that 30 Figure 3.16: Dependance of the on-resistance value of the transmission-gate on the

input voltage value. While maintaing the relation (3.26), the value of WN has been swept from 0.7 µm to 7 µm. can be used to estimate the dominant time constant of the network. Un-

fortunately, in the case studied, this method is not accurate because there

are several poles having comparable frequencies. For this reason, another

approach has been used considering the following assumptions: ' For the LSB sub-array in Figure 3.17, each branch has a time constant whose value is comparable with the others. Hence, as an assumption,

the voltage at the bottom-plate of each capacitor connected to the

pass-transistor providing VCM is considered to be equal during the

transition. Therefore, these nodes can be shorted in the equivalent

circuit and the equivalent impedance of the LSB sub-array will be: ZBP,C s1 '' 1 15sC + RP T,V cm 4 (3.28) The impedance seen from the top-plate of the splitting capacitor Cs1

to VCM is approximately the following: ZT P,C s1 = 1 sC + ZBP,C s1 '' 1 sC + RP T,V cm 4 (3.29) 31 Figure 3.17: Equivalent RC model of the 9-bit DAC for DIN = 256. The resulting equivalent circuit is shown in Figure 3.18. ' At this point, the same assumption can be made once again since the time constants of each branch are still comparable. The bottom-plate

nodes of each capacitor connected to the pass-transistor providing VCM

are shorted together and the final equivalent model is shown in Fig-

ure 3.19. Figure 3.18: Simplified equivalent RC model of the 9-bit DAC for DIN = 256. 32 Figure 3.19: First-order equivalent RC model of the 9-bit DAC for DIN = 256. Now the equivalent model corresponds to a simple first order RC network

and the settling time can be easily estimated. Considering VREF P as refer-

ence voltage, the step response of the voltage node VM is described by the

following expression: VM (t) = VM 0 + VCM + VREF P '' VCM 2 '' VM 0 (1 '' e ''t/' ) (3.30) where VM 0 is the instant voltage value of VM when the digital input is switched from Din=0 to Din=256 and it is equal to: VM 0 = VC M + (VREF P '' VC M ) RP T,V CM 8 RP T,V CM 8 + RP T,V REF P + RT G,BP (3.31) Once the voltage signal VM (t) is settled, it reaches the final value due to the

voltage divider given by the capacitors. Therefore, the difference between

the final and initial voltage is equal to: ''V = VCM + VREF P '' VCM 2 '' VM 0 (3.32) While the time constant of the RC network is calculated as follows: ' = ( RP T,V CM 8 + RP T,V REF P + RT G,BP ) ' 8C (3.33) The settling time is then obtained by considering the time needed by the

output voltage to reach the final value within an error of 0.5LSBs''e , i.e.: VM (tsett) = = 0.5LSBs''e (3.34) 33 From Equation (3.30), the settling time is found as follows: tsett = ''' ln ''V (3.35) Considering minimum-size switches, the settling time tsett,calc estimated

from (3.35) for the worst case of DIN is 12 ns. The ADC presented in

this work reserves approximately 60 ns for the DAC settling time and the

preamplification. In order to relax the requirements on both speed of the

preamplifier and output resistance of the circuit providing the reference volt-

ages, a DAC settling time less than 5 ns is aimed. This can be easily achieved

by increasing the size of the switches in order to reduce their on-resistance,

calculating again the settling time and checking if it is short enough. In this

work the following dimensions have been used: W L P T,VREF N = 6 1 W L P T,VREF P = 18 1 W L T G,BP,N = 6 1 W L T G,BP,P = 18 1 W L P T,VCM = 4 1 where P TV REF N and P TVREF P are the pass-transistors providing VREF N and VREF P respectively, P TV CM is the pass-transistor passing VC M and T GBP,N and T GBP,P the NMOS and the PMOS transistors composing the transmis-

sion gate T GBP . Considering VREF P as reference voltage, the settling time

tsett,calc calculated using Equation (3.35) is 4.10 ns, while the Cadence simu-

lation of the circuit returns tsett,sim = 5.17 ns. Some values calculated using

this method are reported in Table 3.4 and compared with the results given

by the simulation using different switches sizes and both reference voltages.

As shown, it is possible to obtain a first rough estimation of the worst-case

settling time with this method. tsett,calc [ns] tsett,sim [ns] Minimum-size switches

VREF P = 2.65 V 12.00 13.91 VREF N = 0.65 V 11.87 13.15 Chosen switches

VREF P = 2.65 V 4.10 5.17 VREF N = 0.65 V 4.05 5.18 Table 3.4: Calculated and simulated settling time for DIN transiting from 0 to 256. 3.3.3 Other Switches So far, all the bottom-plate switches have been sized except the transmission-

gate T GSig which is directly connected to the input signal. This has been 34 sized to achieve a short settling time and good linearity, which will be further

discussed and analyzed in Section 3.4. Finally, for the top-plate NMOS

pass-transistor which resets the VL node, since low parasitic capacitance are

required on that node (Appendix 5.1), a minimum-size transistor has been

used. The LSB-subarray presents a relatively small equivalent capacitance,

hence even the minimum-size switch is sufficient to perform the reset. The

aspect ratios of the transistors composing these switches are summarized as

follows: W L T G,Sig,N = 10 1 W L T G,Sig,P = 30 1 W L P T,Res = 2 1 3.4 Comparator The comparator is an essential part in the SAR ADC to perform the binary

search algorithm. It has to discriminate voltage values as small as the differ-

ential LSBd''e. In addition, since it is usually the most power-hungry part

of the ADC, a power-efficient solution has to be found during the design. 3.4.1 Overview During the binary search phase, the comparator has to discriminate which

of the MSB sub-array top-plate nodes has higher voltage. This information

is passed then to the SAR logic control which can provide the correct digital

input value for the DAC. Ideally, only one latch is required to perform the

comparison. However, this is not feasible in reality because the latch usually

has a very high offset voltage and can introduce large kickback noise. In this

work, the comparator is composed of two preamplifiers and a latch, as shown

in Figure 3.20. The latch is then loaded with a digital logic that reduces the

metastability effect. Figure 3.20: Structure of the comparator stage. The proposed structure has been chosen for the following main reasons: ' Preamplification is required to overcome the offset voltage of the latch, especially for small input voltage values. ' Offset-cancellation techniques can easily be applied to the preamplifier stage, allowing a correct decision for the comparison. 35 ' The large kickback noise coming from the latch and affecting the ca- pacitive array is reduced due to the presence of the preamplifier. ' There is a minor kickback noise given by the preamplifiers. This can be reduced using two preamplifier stages while limiting the voltage

gain of the first one. 3.4.2 Latch In order to derive the design choices for the preamplifier, the latch stage is

first presented. The dynamic latch [16, 17] shown in Figure 3.21 has been

chosen to reduce the power consumption. When the control signal LatxS is

low, the reset phase is performed and the output nodes are pulled to VDD.

During the regeneration phase, LatxS is set to ''1'' and the circuit determines

which input signal is higher with the aid of the two cross-coupled inverters

M19, M23 and M20, M22. The decision is therefore taken on the rising edge

of the signal LatxS, as shown in Figure 3.22. Figure 3.21: Dynamic latch. Since this latch is dynamic, the power consumption is reduced. This is true

because the latch consumes power only when it is triggered. Otherwise,

during the reset phase, no static current is flowing through it. In addition,

it presents a high speed operation because the NMOS transistors M17-20

immediately enter the active region when the latch is triggered. This is

happening since, immediately after the reset phase, the source node voltages

of M19 and M20 are equal to VDD '' VT while the drain node voltage of M16

is VT below the latch input common mode voltage [18]. 36 Figure 3.22: Output response of the latch for a differential sinusoid input signal. Metastability is an important issue while designing comparators, hence the logic shown in Figure 3.23 has been chosen as load of the latch in order to

limit its influence. During the reset phase (LatxS signal low) the output logic

states Q and Q are kept at the same value, while during the regeneration

phase (LatxS signal high) they provide the output of the result given by the

latch. In case of a metastability error, both output nodes of the latch remain

close to VDD and the output logic maintains the previous values. Hence, the

error due to metastability is bounded in a range equal to ±1 LSBd''e. Figure 3.23: Load of the dynamic latch. Since the input capacitance of the OR gates is approximately 4 fF, the performance of the latch has been tested considering a generic output load

CL of 20 fF in order to have some margin. Considering the maximum transi-

tion of 3.3 V as reference value for the differential output, both regeneration

and reset time have been measured to be always less than 3 ns (Figure 3.24), 37 even for the voltage input as small as 1 LSBd''e. However, given that the

following OR gates can toggle with a smaller than 3.3 V differential output

voltage and the input signal of the latch is already amplified by the previous

stages, enough margin is reserved. Therefore, for the timing diagrams, the

interval between the rising edge of LatxS and a valid output logic state of

Q is chosen to be equal to 3 ns. Figure 3.24: Output response of the latch during the regeneration phase.. The power consumption of the latch can be estimated considering the following formula where IAvg is the average current provided by the power

supply: PLatch,Sim '' VDDIAvg (3.36) Considering that both the regeneration and reset phase are performed ten

times over a 781 ns conversion time and 1''000 cycles are simulated, the esti-

mated power consumption of the latch PLatch,Sim is approximately 7.68 µW. The input-referred offset voltage of the latch, VOS,Latch, has been esti- mated using the test bench [19] shown in Figure 3.25. The common-mode

voltage VCM is applied to an input node of the latch while a ramp signal is

controlling the other one. The ramp signal starts with a value lower than

VCM and increases with 1 mV steps. The regeneration phase is therefore

performed for each voltage level given by the ramp signal. Ideally, the latch

starts toggling when the ramp signal is larger than VCM . In a real circuit,

the corresponding differential input voltage is equal to VOS,Latch instead of

zero, as shown in Figure 3.25. The value of the input-referred offset voltage 38 of the latch is therefore estimated by carrying out a 1''000-runs Monte Carlo

simulation and measuring the differential input voltage. The results are the

following: ' µ(VOS,Latch) = 122 µV ' '(VOS,Latch) = 13.294 mV Figure 3.25: Test bench for the input-referred offset voltage estimation of the latch. Since the standard deviation of VOS,Latch is much larger than its mean value,

an estimation of the input-referred offset voltage value is obtained as follows: VOS,Latch '' 3'(VOS,Latch) = 39.883 mV (3.37) The offset value VOS,Latch of 40 mV will be considered in the forthcoming

calculations. Note, from the above estimation, the preamplifier stage is essential since the smallest differential input to be discriminated by the

comparator should be less than 1 LSBd''e. 3.4.3 Preamplifier Requirements The preamplifier stage is mainly added to suppress the effect of the large

kickback noise and offset voltage from the latch. It is a critical part in this

design, and the following specifications have to be met: ' The preamplifier has to overcome the input-referred offset voltage VOS,Latch of the latch, which is approximately 40 mV. Since the mini-

mum differential input value to be discriminated by the ADC is LSBd''e,

a required voltage gain AV,OS of the preamplifier can be estimated as

follows: AV,OS = VOS,Latch LSBs''e = 40 mV 3.906 mV = 10.23 '' 21 dB (3.38) 39 A 9 dB of margin can be added and thus the minimum voltage gain

AV,min is equal to: AV,min = 21 dB + 9 dB = 30 dB = 32 (3.39) ' Considering 12 cycles for the SAR analog-to-digital conversion (Sec- tion 3.5) and 1.28 MS/s as sampling frequency, each cycle lasts 65 ns.

In addition, reserving approximately 10 ns for both the regeneration

phase of the latch and the settling time of the DAC, the preamplifica-

tion of the input signal has to be performed in a time interval tP reAmp

less than 55 ns. In other words, the minimum differential input value

LSBd''e has to be correctly amplified during tP reAmp. ' The power consumption of the entire ADC should be less than 1 mW, hence reserving half of this value to the preamplifier stage, the maxi-

mum power consumption for this part will be: PP reAmp,max = PADC,max 2 = 500 µW (3.40) ' High values for the input capacitance of the preamplifier result in a large gain error for the DAC (Appendix 5.1). Therefore, the gate-area

of the input transistors has to be minimized. Two-stage preamplifier and kickback noise The preamplifier chosen has two stages and its structure is shown in Fig-

ure 3.26. Since the required minimum gain is not particularly high for this type of structure, diode-connected PMOS transistors have been used as

loads for the first stage while the second stage employs a resistive common-

mode feedback (R-CMFB) circuit [12, 20] where both resistors R are 110 k'.

Therefore, no active common-mode feedback network is required, leading to

a low power consumption. Furthermore, the area occupied by the resistors

is small because the process used provides a high-ohmic resistor option. Since a small unit capacitor is used for the capacitor array, the preampli- fier stage can influence the charge redistribution in the capacitor array due

to its kickback noise. When the input signal is sampled on the top-plate

node (VM ) of the MSB sub-array, this value is immediately amplified by

the preamplifier. However, due to the presence of the gate-to-drain overlap

capacitance CGD1 of the input transistor, the larger variation of the output

voltage of the first preamplifier can affect the node VM through this capaci-

tive path (Figure 3.27). This effect is called kickback noise [21]. If there is a

positive voltage step of VM , the kickback noise effect will decrease this step

size like that in a negative feedback loop. Clearly, the kickback noise also

affects the reference voltages given by the DAC during the binary search. 40 Figure 3.26: Two-stage preamplifier. Figure 3.27: Kickback noise in the first stage of the preamplifier. The analysis with the linear small-signal model of the transistors shows

that the given error is proportional to the voltage gain of the preamplifier,

as expected. Hence, the input voltage values of the comparator should be always scaled by the same factor, avoiding any distortion on the signal.

However, since the range of the input voltage is relatively large (equal to 2 V

considering only one of the two branches), the first stage of the preamplifier

may saturate. In this case, the output response of the preamplifier is not

linear anymore and the kickback noise is causing a distortion on the input

signal and, hence, limiting the linearity of the ADC. For this reason, a two-stage structure has been chosen for the pream- plifier where the first stage has a low voltage gain, which helps to reduce

the error caused by the kickback noise. Note that this design choice allows 41 also the use of small input transistors, leading to a small input capacitance

from the preamplifier as well. The linearity of the sampled signal has been

evaluated with a FFT analysis. For this simulation, a differential sinusoidal

voltage signal has been applied to the input of the ADC with peak-to-peak

amplitude close to F Sd''e and a frequency equal to BWSig. This results in

an SNDR equal to 69.92 dB (ENOB=11.32). Since the value obtained is

larger than 62 dB (ENOB = 10), a sufficient linearity is achieved during the

sampling phase. However, it is preferable to have some margin on this value.

This is obtainable by reducing the effect of the kickback noise even more

with the the capacitive neutralization technique [21, 22]. Since the output

voltages are affecting the input nodes through the gate-drain overlap capac-

itances of the input transistors, it is possible to add two dummy transistors

that approximately present an input capacitance close to CGD1 as shown in

Figure 3.28. To achieve this requirement, the dummy transistors are sized

using the same channel length and half of the width of the input pair M1,

M2: W L Dummy = 1 2 W L 1 (3.41) Therefore, the kickback noise through these overlap capacitances is reduced

and the improvement on the sampling linearity can be checked again with

a FFT analysis that returns an increased SNDR of 81 dB (ENOB=13.21). Figure 3.28: First preamplifier stage with dummy transistors using the capacitive neutralization technique. 42 Offset Cancellation and Sampling The offset of the comparator, which is constant and signal-independent,

causes also an offset of the ADC. This problem can be avoided limiting

or cancelling the offset at the comparator stage. The most famous offset

cancellation techniques [12, 23] are summarized as follows: ' Input offset storage (IOS): two relatively large series capacitors are added to the input nodes of the comparator and the preamplifier is

placed in a unity-gain negative-feedback loop operation. The offset

of the circuit is therefore measured and stored across the capacitors.

The residual input-referred offset voltage after the cancellation is the

following: VOS,Residual = VOS,P reAmp 1 + AV + ''Q C + VOS,Latch AV (3.42) where C is the value of each series capacitor and ''Q the charge-

injection due to the mismatch of the loop switches. As a drawback, this

technique requires a high gain value AV and also a large capacitance

to limit the the charge-injection error. ' Output offset storage (OOS): the series capacitors are now added to the output nodes of the preamplifier and the input nodes of the pream-

plifier shorted together during the offset cancellation. The nodes of the

capacitors not connected to the preamplifier are also shorted together

and thus the amplified offset voltage is stored on the capacitors. The

residual offset is given by the following equation: VOS,Residual = ''Q AV C + VOS,Latch AV (3.43) Hence, the offset of the preamplifier is completely cancelled and the

value of the series capacitor can be chosen smaller than before. How-

ever, since the preamplifier is performing an open-loop amplification,

it should not saturate. For this reason, the voltage gain is usually

limited to be less than 10. ' Active offset cancellation: The main drawback of the previous offset cancellation techniques is that they introduce capacitors in the signal

path. A possible solution is to perform the offset cancellation using an

auxiliary amplifier. The introduced amplifier can sense and subtract

the offset of the stage in a negative feedback loop. Obviously, this

technique is adding a new active element to the circuit, increasing the

overall power consumption. 43 Figure 3.29: Closed-loop operation of the preamplifier performing the input offset storage. In order to achieve a low-power operation for the presented SAR ADC,

the active offset cancellation can be discarded. Also the OOS technique

is not a promising solution because it requires additional output series ca-

pacitors and limits the gain of the preamplifier. Hence, the IOS has been

chosen since the capacitor arrays can be used as input series capacitances

and there is no limitation on the voltage gain. In addition, the entire array

of capacitors present a large equivalent capacitance that reduce the residue

offset caused by the charge injection mismatch, as shown in Equation (3.42),

while providing a sufficient phase margin during the closed-loop operation

of the preamplifier. In order to better understand the offset cancellation technique chosen, the equivalent circuit of the preamplifier placed in the closed-loop operation

is shown in Figure 3.29 where the offset voltage VOS,P reAmp is added and each

capacitive array is replaced with a series capacitor, respectively. Defining

Vin,d and Vout,d as the differential input and output voltage of the entire

preamplifier, the system of equations to be solved is the following: Vout,d = Vin,d Vout,d = (Vin,d + VOS,P reAmp)(''AV ) (3.44) where the DC gain of the preamplifier is equal to ''AV (unity-gain negative-

feedback). Solving the above equations, the result is the following: Vout,d = VOS,P reAmp ''AV 1 + AV (3.45) Referring the value obtained back to the input: Vin,diff = Vout,diff AV = '' VOS,P reAmp 1 + AV (3.46) That is the residual offset voltage of the preamplifier mentioned in Equa-

tion (3.42). At this point, it is possible to have an overview of the whole analog part of the SAR ADC and better understand how both sampling and offset 44 cancellation are performed. The simplified equivalent circuit of the previ-

ous designed circuits is shown in Figure 3.30 and the corresponding timing

diagram is represented in Figure 3.31. Figure 3.30: Simplified equivalent circuit of the analog part of the ADC. In Figure 3.30 the preamplifier stages are represented as ''PreA 1-2''. Ini-

tially, the input signal is applied to the bottom-plate nodes of the capacitive

array, the loop for the offset cancellation is closed and the output nodes

of each preamplifier are shorted together using switches. In this way, each

stage of the preamplifier is reset in a short period of time. After turning

off the ShortOutxS control signal, the loop can effectively perform the off-

set cancellation. Once the loop is open, also the path passing the input

signal can be disconnected and the common-mode voltage is connected to

the bottom-plate of each capacitor in the arrays. In order to correctly per-

form the bottom-plate sampling, the loop switches have to be open before

the switches connected to the input signal, whose charge injection is signal-

dependent. Therefore, any distortion effect is avoided on the sampled signal

at the input nodes of the comparator. Figure 3.31: Sampling timing diagram example. 45 Using the resistive common-mode feedback for the second stage, the top-

plate nodes of the MSB capacitor arrays are correctly reset during the offset

cancellation phase by the closed-loop operation, without the need of other

switches. The reset voltage value VRES for these nodes is approximately

1.70 V while the top-plate nodes of the LSB sub-array are reset to VCM

using two minimum-sized switches. After the signal has been sampled on

the input nodes of the preamplifier, the circuit can start the binary search

algorithm. Design, Analysis and Simulation The optimization of the preamplifier stage requires a thorough study of the

most relevant parameters in order to meet all the requirements. An analyti-

cal analysis has been first conducted and the performances are checked with

Cadence simulations. Considering first the power-speed trade-off, a tail current IT ail of 10 µA is reserved for each stage. The power consumption of the preamplifier is

therefore estimated as follows: PP reAmp '' 2VDDIT ail = 66 µW (3.47) Considering also the bias current, an overall power consumption of 75 µW

can be expected, which is less than the value reserved during the definition

of the requirements. The differential voltage gain AV of the preamplifier is defined as the product of the differential voltage gains of the first and second stage, AV 1

and AV 2 respectively: AV = AV 1AV 2 (3.48) where the differential gain of each preamplifier stage is approximately the

following: AV 1 = gm1 gm3 + gds1 '' gm1

gm3 (3.49) AV 2 = gm7 gds9 + 1 R + gds7 '' gm7R (3.50) where gm is the transconductance and gds the output conductance of the

transistors. The input transistors of both stages are operated in moderate

inversion to improve the values of the respective transconductances while all

the other transistors are operated in strong inversion. Since the input capacitance of the latch is approximately 4 fF, the circuit has been simulated in Cadence considering a generic capacitive output load

CL of 20 fF to have some margin. The results obtained are summarized in

Table 3.5 while the magnitude and phase diagrams of the open-loop transfer

function is shown in Figure 3.32. 46 Parameter Value AV 30.57 dB f''3 dB 33.54 MHz GBW P 1.13 GHz Power 72.60 µW Table 3.5: Preamplifier specifications. Figure 3.32: Magnitude and phase diagrams of the open-loop preamplifier transfer function. The speed of the preamplifier is another important requirement to be considered during the design. Considering that a bit decision has to be taken

approximately every 65 ns, the input signal should be correctly preamplified

in a time interval tP reAmp less than 55 ns. Applying a step input voltage

equal to LSBd''e, which is the minimum input value to be discriminated,

the differential output voltage reaches 129.4 mV after only 20 ns. Hence, the

input signal is sufficiently amplified in a short time interval since the output

reaches a value larger than the input-referred offset voltage of the latch.

Obviously, higher input values will achieve the requirements even faster. The

step responses of the differential outputs for both the preamplifier stages are

shown in Figure 3.33. When the noise is considered, the first stage of the preamplifier is an- alyzed since it is the major contributor. Both thermal and flicker (1/f ) 47 Figure 3.33: Step responses of the preamplifier stages for a LSBd''e differential

input. The blue trace represents the differential output voltage of the first stage, while the red trace shows the differential output voltage of the second stage. input-referred voltage noises can be estimated respectively as follows: e2 T hermal,in = 8kBT γ gm1 1 + gm3

gm1 (3.51) e2 F licker,in = 2K (1/f ) n CoxW1L1 1 f + 2K (1/f ) p CoxW3L3 1 f gm3 gm1 2 (3.52) where kB is the Boltzmann constant, T the temperature expressed in Kelvin,

K(1/f) a constant that depends on the technology, f the frequency, and γ a

coefficient which is around 2

3 for long channel devices and can be larger for deep sub-micron CMOS technologies. In order to evaluate the performance

of the circuit, the noise of the entire preamplifier can be integrated over

its frequency bandwidth and referred back to the input. In this way, it

is possible to compare it with the 0.5LSBd''e reference value. The noise

bandwidth is the following: BWNoise = ' 2 f''3 dB = 52.68 M Hz (3.53) where f''3 dB is the bandwidth of the preamplifier stage. In order to have

some margin, a noise bandwidth BWNoise equal to 1 GHz has been consid-

ered during the simulation. The integrated input-referred RMS value of the

noise of the stage is: ['Noise,in] 1 GHz

1 Hz = ['Noise,out] 1 GHz

1 Hz AV = 138.33 µVRMS (3.54) 48 where ['Noise,out] 1 GHz

1 Hz is the RMS value of the noise at the output nodes of the stage integrated on the 1 GHz bandwidth. Therefore, it is possible

to estimate the input-referred noise and compare it with the 0.5LSBd''e

reference value as follows: VNoise,P reAmp '' 3 ['Noise,in] 1 GHz

1 Hz = 415.00 µV 0.5LSBd''e (3.55) Since VNoise,P reAmp is much less than the 0.5LSBd''e reference value, the

stage has a good noise performance. Statistic offset voltage can affect the performance of the preamplifier and hence of the entire ADC. The input-referred offset voltage of the first stage

can be estimated as follows: VOS,P reAmp = VOS,1 + VOS,3 gm3

gm1 (3.56) where VOS,1 and VOS,3 are the variables representing the equivalent statistic

offset voltage values of M1, M2 and M3, M4 respectively. The variance of

these variables can be found as follows: ' 2(V OS ) = ' 2(''V T ) + ' 2 ''β β ID gm 2 (3.57) where ''VT and ''β represent the threshold voltage and current factor mis-

match respectively. Using Pelgrom coefficients [24, 25]: '(''VT ) = AV T '' W L (3.58) ' ''β β = Aβ '' W L (3.59) From a 1''000-runs Monte Carlo simulation, the input-referred offset voltage

VOS,P reAmp is estimated as follows: VOS,P reAmp '' 3'(''VOUT ) AV = 20.66 mV (3.60) where ''VOUT is the difference between the DC values of VopA and VonA.

Since the offset voltage of the preamplifier stage is larger than LSBd''e, an

offset cancellation technique is required. The chosen input offset storage

technique returns the following residual input-referred offset voltage after

the cancellation: VOS,Residual = VOS,P reAmp 1 + AV = 594.40 µV (3.61) Again, this residual voltage value can be compared to the 0.5LSBd''e reference value and note that the smallest differential input signal can be

therefore estimated after the cancellation. 49 The offset cancellation is performed in an unity-gain negative-feedback loop configuration during the sampling phase, hence, the stability of the

stage has to be checked. The preamplifier reaches a phase margin P M of

78.40' during the closed-loop mode, providing a safe margin for the stability.

Due to the large equivalent capacitance at the input nodes of the comparator

provided by the capacitive array, the first dominant pole of the loop gain

transfer function is shifted towards low frequencies, improving the stability

of the system. The magnitude and phase diagram of the loop gain are shown

in Figure 3.34. Figure 3.34: Magnitude and phase diagrams of the loop gain transfer function. 3.5 SAR Control Logic A control logic is required to control both the S/H and the DAC, to fi-

nally perform the binary search algorithm. Once the latch has made its

decision, the result is stored in the register and the DAC digital input is up-

dated according to the decision. During this closed-loop operation, timing

requirements have to be met and, again, low-power solutions are preferred. 3.5.1 Timing Diagrams Since 16 ADCs are going to be implemented in the chip, a sampling fre-

quency fs of 1.28 MHz has been chosen during the elaboration of specifica-

tions in Section 2.2. Therefore, each ADC has a conversion time tconv equal 50 to: tconv = 1 fs '' 781 ns (3.62) One analog-to-digital conversion is carried out in 12 clock cycles as designed

in this work. While the first cycle is reserved to reset the output voltage of

the comparator stages, the second one is used to sample the input signal.

The remaining 10 cycles are required for the 10-bit conversion. Therefore,

for each cycle the following time interval tcycle is needed: tcycle = tconv 12 '' 65 ns (3.63) Hence, a master clock frequency fclk equal to 15.36 MHz is required. The

timing diagrams of the conversion are represented in Figure 3.35. All the

digital control signals are generated from the master clock signal ClkxC

and a second clock signal ClkdxC which is delayed by 3 ns with respect

to ClkxC. Note that the digital signal ClkdxC is mostly used to generate

the short pulses that trigger the latch and allows the circuit to perform the

bottom-plate sampling. Moreover, the digital signal ShortOutxS is high to

short the output nodes of each preamplifier, LoopxS is the control signal

that closes the loop, SelInxS becomes high when the input signal is applied

to the capacitive array, DIN is the digital input of the DAC and LatxS is

the control signal for the latch. The signal DigOutxS represents the first

9 bits of the output digital value while SignxS is the MSB (sign bit). It is

important to observe that DIN is equal to DigOutxS when its first 8 bits

are determined (from cycle #4 to cycle #12) but it is reset at the beginning

of the new conversion. The value of the last bit of DigOutxS is instead

assigned at this time, therefore the 10-bit output digital value is ready to be

saved in a register during cycle #2, when the end-of-conversion signal EocxS

is high. During the first cycle the preamplifier stages are reset, as indicated

from the digital control signal ShortOutxS that is set to ''1''. The input

signal is effectively sampled on the bottom-plate nodes of the capacitors in

the second cycle since LoopxS and SelInxS are both high. At this time the

preamplifier is operating in closed-loop, hence also the offset cancellation is

performed. LoopxS is set to ''0'' before the ending of the cycle in order to

realize the bottom-plate sampling. At the third cycle, all the bottom-plate

nodes of the capacitors are connected to the common voltage (DIN equal

to ''0'') and the sampled charge is redistributed on the input nodes of the

comparator. The first comparison can be therefore executed and the MSB

is determined at the beginning of the fourth cycle when the latch is triggered.

The timing diagrams of the first three cycles are shown in Figure 3.36.

At the beginning of the cycle #4 the reference voltages (VREF P and VREF N )

are assigned to the corresponding capacitor arrays depending on the result of

the last comparison and the DAC input signal is set to its half-range value.

Hence, the cycles from #4 to #12 are used to determine the remaining 9 51 Figure 3.35: Timing diagrams of the SAR control logic. 52 Figure 3.36: Timing diagrams for the first three cycles of a conversion. bits with the binary search algorithm. In particular, at the beginning of

each cycle, each DAC provides a new voltage value based on the previous

bit-decision, while the preamplifier amplifies the difference between its input

nodes and the latch makes a decision once it is triggered (when the LatxS

signal goes high). On the new cycle, the digital input DIN of the DAC will

be eventually updated depending on the previous comparison result and

a new voltage value will be provided. A part from the fourth cycle, the

remaining cycles are clearly all equal, as shown in Figure 3.37 where cycles

#4, #5 and #6 are illustrated. 3.5.2 SAR Control Logic Implementation The digital part of this ADC has been implemented as a successive approx-

imation register (SAR) whose simplified structure is shown in Figure 3.38.

Two rows of flip-flops are used to generate the digital input signal DIN for

the DAC: the first row is a shift register that shifts a logical ''1'' while each

flip-flop of the second row is first set to logical ''1'' and then is eventually reset 53 Figure 3.37: Timing diagrams of the cycles used to determine the last 9 bits of the digital output. to logical ''0'', depending on the result of the comparison given by the signal

CompxS. The solution presented is quite popular in SAR ADCs [26, 27]

and it based on the design proposed in [28]. Considering the entire chip that

will host the 16 SAR ADCs, the shift register can be shared among them in

order to reduce both overall area and power consumption. 3.5.3 Delay Elements A second clock signal delayed by 3 ns is required by the SAR control logic

and it is generated using a chain of inverters accurately sized. In order

to increase the delay, as shown in Figure 3.39, the chain consists of two

inverters using transistors with larger length L equal to 4.2 µm and two

minimum-sized inverters added both to the input and the output of the

chain. This design choice allows to have larger output resistance for the

sized inverters, increasing the time delay while minimizing the capacitive

load for the driving circuit. The first two minimum-sized inverters are used

to drive the structure while the last two one allow the circuit to achieve 54 Figure 3.38: Successive approximation register for binary search. shorter rise and fall time. A generic output load CL of 10 fF has been used

to evaluate the time delay tD, the 10%-to-90% rise time tR, the 90%-to-10%

fall time tF and the dynamic power consumption. Simulating the circuit,

the values obtained are the following: a delay time tD of 3.446 ns is achived,

rise time and fall time are respectively equal to 248 ps and 186 ps, while the

power consumption is equal to 21.043 µW. Nevertheless, this block can be

shared among all the ADCs present on chip. Figure 3.39: Chain of inverters to generate the delayed clock signal. 3.6 Layout The layout of the entire SAR ADC is shown in Figure 3.40. The dimen-

sions of this block are 395 ' 391 µm2, leading to an overall area AADC of

1540445 µm2. The floorplan is illustrated in Figure 3.41 where the different

parts have been highlighted. These parts are the two capacitive arrays and

their relative switches, the comparator and the digital part required for each

ADC. As expected, the capacitive array occupies the largest amount of area

among all blocks. The layout has been conducted while in a way to make 55 Figure 3.40: Floorplan of the SAR ADC. a compact structure. However, the analog part has been placed at a safety

distance of approximately 100 µm from the digital circuits to reduce the

coupling noise coming through the substrate [29].

Some of the digital part of the ADC is shared among all the ADCs on chip

(Section 3.5) and its layout is shown in Figure 3.42. The dimensions of this

part are 142 ' 87 µm2, for an area ADigShared of 12 0354 µm2. Considering again the implementation of all the SAR ADCs on chip, at this point it is possible to estimate the overall required area. One possible

floorplan for the MEA chip is to place 1''024 read-out channels on two sides

of the chip, i. e., 512 channels are reserved for each side. Thus, the 16 SAR

ADCs can also be split in two groups while adding the digital shared logic

to each of them. The floorplan of the ADCs implemented on chip is shown

in Figure 3.43. Hence, the overall area required on chip can be estimated as

follows: AADC,Chip = 16AADC + 2ADigShared '' 2.50mm 2 (3.64) 56 Figure 3.41: Analog and digital blocks composing the SAR ADC. Figure 3.42: Layout of the shared digital logic among all the ADCs on chip. Figure 3.43: Floorplan of the ADCs integrated on the MEA chip. 57 Chapter 4 Simulations and Conclusions 4.1 Simulation Results In order to evaluate the performance of the designed circuit, the charac-

terization of the SAR ADC has to be conducted running different post-

layout simulations. First of all, an example of analog-to-digital conversion

is presented in Figure 4.1 where the reported voltage signals are measured

at the input nodes of the preamplifier (VipA and VinA). Both the sign-bit

SignxS and the remaining 9 bits DigOutxS composing the digital output

are shown as well. The conversion has been done for a constant analog input

value whose amplitude is equal to the differential full-scale F Sd''e. Hence,

the SAR ADC provides the highest value for the digital output. Note that

SignxS is equal to ''1'' if the differential input voltage is positive, while the

remaining 9 bits are given by DigOutxS. Differential and integral linearity errors (DNL and INL respectively) can be evaluated using the histogram test with a linear ramp input [4]. In this

kind of simulation consists a large number of digitized samples is collected

from the ADC for an input signal with known probability density function,

such as a linear ramp. From the simulation results, both DNL and INL

histogram plots can be derived and they are shown in Figures 4.2 and 4.3

respectively. Both DNL and INL errors are less than 0.5 LSBd''e for each

digital output. The resolution of the presented linearity analysis is equal to

0.05 LSBd''e. A 2''048-points FFT analysis is run to evaluate both the SNDR and SFDR of the converter. The sampling frequency fs is set to 1.28 MS/s

while the frequency of the input sinusoidal wave is close to 10 KHz which is

the bandwidth BWsig of the neural signals. The output of the FFT analysis

is a power spectral density graph and is shown in Figure 4.4. The SFDR

measured is 76.51 dB while the SNDR reaches 60.74 dB that leads to an

ENOB of 9.79. The power consumptions of both analog and digital parts of the ADC 58 Figure 4.1: Example of an analog-to-digital conversion performed by the SAR ADC. Figure 4.2: DNL histogram plot of the SAR ADC. are finally measured. Note, the digital control logic is divided into two parts:

one part is added to each converter (Digital) while the other one is shared

all the ADCs (Shared digital) present on chip, as explained in Section 3.6.

For this reason, in Table 4.1 the two different digital power consumptions

are distinguished.

For the MEA chip application, the overall power consumption of the ADCs

is therefore estimated as follows: PT ot = 16(PAnalog + PDigital) + 2PSharedDigital = 2.25 mW (4.1) Altough the proposed data converter is not supposed to be general-purpose, 59 Figure 4.3: INL histogram plot of the SAR ADC. Figure 4.4: 2''048-points FFT output of the SAR ADC. Part Power [µW ] Analog 95.24 Digital 31.88 Shared digital 105.80 Table 4.1: Summary of the ADC power consumption. its power efficiency can be estimated with the following figure of merit: F oM = PADC 2ENOBfS (4.2) 60 where PADC is the total power consumption of one ADC and, for the case

presented, is estimated as: PADC = PT ot 16 = 140.63 µW (4.3) That leads to a FoM of 125 fJ/conv-step. Note that this figure of merit is

calculated without considering the power consumptions of the multiplexers

and buffers required by the system. Table 4.2 summarizes and compare both the requirements and the es- timated specifications for the designed SAR ADC. In addition, the perfor-

mance of the proposed data-conversion system that can be integrated on

the MEA chip is shown in Table 4.3. These results are compared with the

specifications of the single-slope ADCs currently integrated on the latest

version of the MEA chip. Parameter Requirements Estimated values Resolution 10 bits Sampling Rate 1.28 MS/s Supply Voltage 3.3 V Full Scale Range 2.0 Vpp (differential) DNL < 0.5 LSB + 0.35 / - 0.35 LSB INL < 1 LSB + 0.35 / - 0.35 LSB ENOB 9 bits 9.79 bits SNDR ' 56 dB 60.74 dB SFDR - 76.51 dB Area ' 1 mm2 0.157 mm2 Power Consumption ' 1 mW 140.7 µW Technology 0.35 µm CMOS Table 4.2: Requirements and estimated performance of a single SAR ADC. ADC Single-Slope SAR Resolution 10 bits ENOB 9.7 bits 9.79 bits Area 7.04 mm2 2.50 mm2 Analog Power Consumption 6.19 mW 1.53 mW Table 4.3: Specifications of the single-slope data-conversion system currently im- plemented on chip, compared to the performance of the SAR ADCs. 61 4.2 Conclusions The presence of integrated analog-to-digital converters on chip is an essential

requirement for allowing a good signal transmission between the chip and

the external devices. After comparing the most relevant topologies for data

converters, the SAR ADC has been chosen since it is a promising solution

that could meet the required specifications by multiplexing the read-out

channels on the MEA chip. Both low power consumption and low complexity

of the circuit are relevant advantages of the chosen ADC and key aspects to

succeed in the design. Switched-capacitor arrays are used to implement both the S/H and DAC while minimizing the value of the unit capacitor. The arrays are split in two

parts to reduce the overall equivalent capacitance which is equal to 6.05 pF

for a unit capacitor of only 64.36 fF. The capacitance provided by this part

can be used to store the offset voltage of the preamplifier and cancel its

effect on the ADC performance. In fact, the residual input-referred offset

voltage of the amplifier is 594.40 µV after the cancellation, that is largely

less than the LSB value. While considering the timing requirements, the

sizes of the switches are optimized to reduce their area. In this work, the

switches occupy only 1.72 % of the total area of the ADC. A low-power

two-stage preamplifier is designed to improve the efficiency of the compar-

ison and drive the input nodes of the latch. In fact, the preamplifier can

overcome the large offset voltage of the latch, that is estimated to be 40 mV

in the worst case. Moreover, the effect of the kickback noise caused by

the preamplifier is reduced by using the capacitive neutralization technique,

leading to ENOB of 13.21 for the linearity quality of the sampling. The dig-

ital part is implemented adopting a successive approximation register whose

shift register is shared among all the ADCs present on chip, therefore saving

the 67.23 % of the digital power consumption. The ADC occupies an area of 0.157 mm2 and presents an overall power consumption of 140.63 µW for a sampling frequency of 1.28 MS/s. From

the post-layout simulation results, both DNL and INL errors are bounded

in a 0.35 LSB range. Concerning the linearity of the ADC, an ENOB of

9.79 is obtained. The power efficiency is estimated with the FoM defined

in (4.2), that is equal to 125 fJ/conv-step. Finally, comparing this simulation

results with the specifications of the single-slope ADCs currently integrated

on the latest version of the MEA chip, the proposed data-conversion system

presents an improvement of 64.49 % in terms of area reduction and its analog

power consumption is 4 times less. In conclusion, the presented SAR ADC has proved to be a promising solution for low-power applications. All the preliminary requirements have

been met and a good performance achieved. The specifications of the data-

conversion system have been compared with the ADCs currently imple-

mented on the MEA chip and a possible improvement of its performances 62 has been presented. The designed circuit is therefore ready to be integrated

on chip for a final characterization based on real measurements. 63 Chapter 5 Appendix 5.1 Effects of the parasitic capacitances in the DAC The equivalent circuit of the switched-capacitor DAC is shown in Figure 5.1

where m and p are the sums of the unit capacitors connected in parallel

to the reference voltage in the LSB sub-array and MSB sub-array respec-

tively (Section 3.2). In addition, the parasitic capacitances affecting both

VL and VM nodes, Cp1 and Cp2 respectively, are added to the equivalent

circuit. While Cp1 is the bottom-plate parasitic capacitance of the series

capacitor C, Cp2 represents the gate capacitance of the input transistors of

the comparator. Figure 5.1: Switched-capacitor DAC equivalent circuit. Considering first the ideal case where no parasitic capacitances are present in the circuit (Cp1 = 0 and Cp2 = 0) and assuming that all the capacitors

are discharged before applying the digital input signal, the equations given 64 by the charge conservation principle are the following: 0 = mC(VL '' VREF P ) + (15 '' m)C(VL '' VCM ) + C(VL '' VM ) 0 = pC(VM '' VREF P ) + (31 '' p)C(VM '' VCM ) + C(VM '' VL) Solving the previous system of equations, the output voltage VM of the DAC

is: VM = VCM + (VREF P '' VCM ) m + 16p 511 (5.1) If the parasitic capacitances are taken into account, the previous system of

equations is modified as follows: Cp1(VCM '' VDD) = mC(VL '' VREF P ) + (15 '' m)C(VL '' VCM ) + +C(VL '' VM ) + Cp1(VL '' VDD) Cp2(VCM '' VDD) = pC(VM '' VREF P ) + (31 '' p)C(VM '' VCM ) + +C(VM '' VL) + Cp2(VM '' VDD) that results in the following output voltage VM for the DAC: VM = VCM + (VREF P '' VCM ) m + 16p + pCp1 511 + 32Cp1 + 16Cp2 + Cp1Cp2 (5.2) It is therefore possible to study the influence of the parasitic capacitances

on the DAC by comparing (5.2) with (5.1). In fact, while both parasitic

capacitances are introducing a gain error, only Cp1 is causing a distortion

on the DAC, hence limiting its linearity. Finally, note that, since the gate

capacitance Cp2 is usually larger than Cp1, the gain error is mostly given by

the gate capacitance of the comparator''s input transistors. 5.2 Standard deviation estimation of the DAC out-

put voltage Considering a simple 3-bit binary-weighted switched-capacitor DAC, the

analytical estimation of the standard deviation for its output voltage is pre-

sented in this section. The capacitive array and the equivalent circuit are

shown in Figure 5.2. The output voltage of the 3-bit DAC for the half-range

digital input code (DIN = 4 = 100) presents the worst case in terms of

mismatch among the capacitors [11], hence the constriction on the standard

deviation of this voltage should satisfy the following condition: 3'(VM,D IN =4) ' 0.5LS B (5.3) 65 Figure 5.2: 3-bit switched-capacitor DAC and its equivalent circuit. Defining Ceq=C+C+2C, the output voltage value for the half-range digital

input code is the following: VM,D IN =4 = VC M + (VREF P '' VC M ) 4C 4C + Ceq = 2.15 V (5.4) Considering the capacitances as independent random variables, the mean

value of VM,D IN =4 is: µ(VM,D IN =4) = 2.15 V (5.5) On the other hand, the calculation of the standard deviation '(VM,D IN =4) requires more steps. Calculating first both the mean value and the variance

of the equivalent capacitance Ceq: µ(Ceq) = µ(C) + µ(C) + µ(2C) = 4µ(C) ' 2(C eq ) = ' 2(C) + '2(C) + '2(2C) = 4'2(C) Adding the value of the MSB capacitance 4C: µ(4C + Ceq) = µ(4C) + µ(Ceq) = 8µ(C) ' 2(4C + C eq ) = ' 2(4C) + '2(C eq ) = 8' 2(C) Hence, the variance of the capacitive-divider ratio is: ' 2 4C 4C + Ceq = µ(4C) µ(4C + Ceq) 2 '2(4C) µ2(4C) + '2(4C + Ceq)

µ2(4C + Ceq) 2 = 3'2(C) 32µ2(C) The variance of VM,D IN =4 is therefore found as follows: ' 2(V M,DIN =4) = ' 2 VCM + (VREF P '' VCM ) 4C 4C + Ceq = = (VREF P '' VCM ) 2 3' 2(C) 32µ2(C) 66 Writing µ(C) as µC and '(C) as 'C, the standard deviation of VM,D IN =4 is the following: '(VM,D IN =4) = (VREF P '' VC M ) '' 6'C 8µC (5.6) Since both µC and 'C depend on the area of the unit capacitor, by substi-

tuting the parametric expressions in (5.3), one can determine the minimum

unit capacitor area that satisfies the condition. 67 Bibliography [1] A. Hierlemann, U. Frey, S. Hafizovic et al., ''Growing cells atop micro- electronic chips: Interfacing electrogenic cells in vitro with CMOS-based

microelectrode arrays,' Proc. IEEE, vol.99, pp.252-284, Feb. 2011. [2] U. Frey, J. Sedivy, F. Heer et al., ''Switch-matrix-based high-density mi- croelectrode array in CMOS technology,' IEEE J. Solid-State Circuits,

vol.45, pp.467-482, Feb. 2010. [3] R. R. Harrison, ''The Design of Integrated Circuits to Observe Brain Activity,' Proc. IEEE, vol.96, no.7, pp.1203-1216, Jul. 2008. [4] W. Kester, ''The Data Conversion Handbook,' Analog Devices, Inc., 2005. [5] J. L. McCreary and P. R. Gray, ''All-MOS charge redistribution analog- to-digital conversion techniques-Part I,' IEEE J. Solid-State Circuits,

vol.SC-10, no.6, pp.371-379, Dec. 1975. [6] R. J. Baker, ''CMOS Circuit Design, Layout and Simulation,' Wiley- IEEE Press, 2010. [7] B. Razavi, ''Data Conversion System Design,' IEEE Press, 1995. [8] C. Liu, S. Chang, G. Huang and Y. Lin, ''A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,' IEEE J. Solid-State

Circuits, vol.45, no.4, pp.731-740, Apr. 2010. [9] L. Cong, ''Pseudo C-2C ladder-based data converter technique,' Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transac-

tions on, vol.48, no.10, pp.927-929, Oct. 2001. [10] S. Haenzsche, S. Henker and R. Schuffny, ''Modelling of capacitor mis- match and non-linearity effects ini charge redistribution SAR ADCs,'

Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Pro-

ceedings of the 17th International Conference, pp.300-305, 24-26 Jun.

2010. 68 [11] Z. Lin, H. Yang, L. Zhong, J. Sun and S. Xia, ''Modeling of capacitor array mismatch effect in embedded CMOS CR SAR ADC,' ASIC, 2005.

ASICON 2005. 6th International Conference On, vol.2, no., pp.982-986,

24-27 Oct. 2005. [12] B. Razavi, ''Design of Analog CMOS Integrated Circuits,' McGraw- Hill, 2001. [13] A. Agnes, E. Bonizzoni, P. Malcovati and F. Maloberti, ''A 9.4 EnoB, 1V, 3.8uW, 100kS/s SAR-ADC with Time-Domain Comparator,' IEEE

International Solid-State Circuits Conference (ISSCC), 2008. [14] N. H. E. Weste and D. M. Harris, ''CMOS VLSI Design: A Circuits and Systems Perspective,' Addison-Wesley, Fourth Edition, 2011. [15] A. Hastings, ''The Art of Analog Layout,' Prentice Hall, Second Edi- tion, 2006. [16] T. Kobayashi, K. Nogami, T. Shirotori and Y. Fujimoto, ''A current- controlled latch sense amplifier and a static power-saving input buffer

for low-power architecture,' Solid-State Circuits, IEEE Journal, vol.28,

no.4, pp.523-527, Apr. 1993. [17] S. Cho, C. Lee, J. Kwon and S. Ryu, ''A 550-µW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction,' Solid-

State Circuits, IEEE Journal, vol.46, no.8, pp.1881-1892, Apr. 2011. [18] K. Y. Kim, ''A 10-bit, 100 MS/s Analog-to-Digital Converter in 1- µm CMOS,' PhD Thesis, Integrated Circuits & Systems Laboratory

Electrical Engineering Department, University of California, Jun. 2006. [19] A. Graupner, ''A Methodology for the Offset Simulation of Com- parators,' The Designer''s Guide Community, www.designers-guide.org,

2006. [20] B. Song, M. Choe, P. Rakers and S. Gillig, ''A 1 V 6 b 50 MHz current- interpolating CMOS ADC,' VLSI Circuits, 1999. Digest of Technical

Papers. 1999 Symposium, pp.79-80, 1999. [21] P. M. Figueiredo and J. C. Vital, ''Low kickback noise techniques for CMOS latched comparators,' Circuits and Systems, 2004. ISCAS ''04.

Proceedings of the 2004 International Symposium, vol.1, pp.I- 537-40

Vol.1, May 2004. [22] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, ''Analysis and Design of Analog Integrated Circuits,' John Wiley & Sons, INC., Fourth

Edition, 2001. 69 [23] B. Razavi and B. A. Wooley, ''Design techniques for high-speed, high- resolution comparators,' Solid-State Circuits, IEEE Journal, vol.27,

no.12, pp.1916-1926, Dec. 1992. [24] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, ''Match- ing properties of MOS transistors,' Solid-State Circuits, IEEE Journal,

vol.24, no.5, pp. 1433- 1439, Oct. 1989. [25] P. R. Kinget, ''Device mismatch and tradeoffs in the design of analog circuits,' Solid-State Circuits, IEEE Journal, vol.40, no.6, pp. 1212-

1224, Jun. 2005. [26] M. D. Scott, B. E. Bose and K. S. J. Pister, ''An ultralow-energy ADC for Smart Dust,' Solid-State Circuits, IEEE Journal, vol.38, no.7, pp.

1123- 1129, Jul. 2003. [27] Y. Zhu, C. Chan, U. Chio, S. Sin, S. Sin, S. U, R. P. Martins and F. Maloberti, ''A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm

CMOS,' Solid-State Circuits, IEEE Journal, vol.45, no.6, pp.1111-1121,

Jun. 2010. [28] T. O. Anderson, ''Optimum Control Logic for Successive Approxima- tion Analog-to-Digital Converters,' Comput. Design, vol.11, no.7, pp.81-

86, Jul. 1972. [29] D. K. Su, M. J. Loinaz, S. Masui and B. A. Wooley, ''Experimental results and modeling techniques for substrate noise in mixed-signal in-

tegrated circuits,' Solid-State Circuits, vol.28, no.4, pp.420-430, Apr.

1993. 70

Politecnico di Milano for his continuous support and for making my stay

at ETH Z¨ urich. I am particularly grateful to Prof. Andreas Hierlemann who gave me the unique opportunity to carry out my Master''s Thesis at his

laboratory. Dr. Yihui Chen deserves special thanks for his intelligent guid-

ance through the world of the analog-to-digital converters. I also would like

to express my gratitude to Pascal Meinerzhagen for his helpful suggestions

and to Vijay Viswam for his insightful comments during the completion of

the project. I was truly fortunate to have the possibility to work at the Bio

Engineering Laboratory (BEL) and I owe sincere thanks to all the people I

worked with. 3 Contents 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 MEA Chips Developed at BEL . . . . . . . . . . . . . . . . . 1 1.2.1 Interfacing Electrogenetic Cells in Vitro with CMOS

Microelectrode Arrays . . . . . . . . . . . . . . . . . . 1 1.2.2 The High-Density MEA Chip . . . . . . . . . . . . . . 3 1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . 5 2 Specifications and ADC Topologies 6 2.1 Required ADC for the New Version of the Chip . . . . . . . . 6 2.2 Elaboration of Specifications . . . . . . . . . . . . . . . . . . 6 2.3 Low Power ADC Topologies Overview . . . . . . . . . . . . . 7 2.4 Fully Differential Switched-Capacitor SAR ADC . . . . . . . 10 3 Design implementation 13 3.1 Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Switched-Capacitor Array . . . . . . . . . . . . . . . . . . . . 13 3.2.1 Capacitive Array Design . . . . . . . . . . . . . . . . . 17 3.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.1 Switch Structures . . . . . . . . . . . . . . . . . . . . . 27 3.3.2 DAC Settling Time . . . . . . . . . . . . . . . . . . . . 30 3.3.3 Other Switches . . . . . . . . . . . . . . . . . . . . . . 34 3.4 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.2 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.3 Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . 39 3.5 SAR Control Logic . . . . . . . . . . . . . . . . . . . . . . . . 50 3.5.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . 50 3.5.2 SAR Control Logic Implementation . . . . . . . . . . 53 3.5.3 Delay Elements . . . . . . . . . . . . . . . . . . . . . . 54 3.6 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 4 Simulations and Conclusions 58 4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5 Appendix 64 5.1 Effects of the parasitic capacitances in the DAC . . . . . . . . 64 5.2 Standard deviation estimation of the DAC output voltage . . 65 Bibliography 68 5 List of Figures 1.1 Packaged MEA chip on a custom-designed printed circuit board. 2 1.2 (a) Schematic of a cell attached to a sensor surface. (b) Mi-

crograph of an acute cerebellar brain slice (parasagittal cut)

placed on a CMOS high-density electrode chip for measure-

ments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Micrograph of the MEA chip (7.5 ' 6.1 mm2). . . . . . . . . 3 1.4 Block diagram of the MEA chip. . . . . . . . . . . . . . . . . 4 2.1 Single-slope ADC [4]. . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Successive-approximation ADC structure [4] and a 4-bit analog-

to-digital conversion. . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 First-order sigma-delta ADC [4] . . . . . . . . . . . . . . . . . 9 2.4 3-bit single-ended switched-capacitor SAR ADC. . . . . . . . 10 2.5 4-bit fully differential switched-capacitor SAR ADC. . . . . . 11 2.6 Voltages at VipA and VinA during the sampling and conversion

phases for the 4-bit fully differential switched-capacitor SAR

ADC [8]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Binary weighted switched-capacitor array. . . . . . . . . . . . 15 3.2 Binary weighted switched-capacitor array equivalent circuit. . 16 3.3 2bw1Cs capacitive array. . . . . . . . . . . . . . . . . . . . . . 16 3.4 5bw4Cs capacitive array. . . . . . . . . . . . . . . . . . . . . . 16 3.5 C2C capacitive array. . . . . . . . . . . . . . . . . . . . . . . 16 3.6 2bw1Cs switched-capacitor array with the bottom-plate par-

asitic capacitance added. . . . . . . . . . . . . . . . . . . . . . 18 3.7 2bw1Cs switched-capacitor array equivalent circuit. . . . . . . 19 3.8 INL graph estimation of each split capacitive array. . . . . . . 20 3.9 Modified split capacitive array. . . . . . . . . . . . . . . . . . 23 3.10 Modified split capacitive array equivalent circuit. . . . . . . . 23 3.11 Floorplan of the capacitive array. . . . . . . . . . . . . . . . . 25 3.12 INL graphs of the 9-bit DAC comparing two different values for the unit capacitance. . . . . . . . . . . . . . . . . . . . . . 25 3.13 Capacitive array with ideal bottom-plate and top-plate switches. 28

3.14 Mux-like structure for the switches of the capacitive array. . . 29 6 3.15 Shared-block structure for the switches of the capacitive array. 29

3.16 Dependance of the on-resistance value of the transmission- gate on the input voltage value. While maintaing the rela-

tion (3.26), the value of WN has been swept from 0.7 µm to

7 µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.17 Equivalent RC model of the 9-bit DAC for DIN = 256. . . . . 32 3.18 Simplified equivalent RC model of the 9-bit DAC for DIN = 256. 32

3.19 First-order equivalent RC model of the 9-bit DAC for DIN = 256. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.20 Structure of the comparator stage. . . . . . . . . . . . . . . . 35 3.21 Dynamic latch. . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22 Output response of the latch for a differential sinusoid input signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.23 Load of the dynamic latch. . . . . . . . . . . . . . . . . . . . 37 3.24 Output response of the latch during the regeneration phase.. 38 3.25 Test bench for the input-referred offset voltage estimation of the latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.26 Two-stage preamplifier. . . . . . . . . . . . . . . . . . . . . . 41 3.27 Kickback noise in the first stage of the preamplifier. . . . . . 41 3.28 First preamplifier stage with dummy transistors using the capacitive neutralization technique. . . . . . . . . . . . . . . . 42 3.29 Closed-loop operation of the preamplifier performing the in- put offset storage. . . . . . . . . . . . . . . . . . . . . . . . . 44 3.30 Simplified equivalent circuit of the analog part of the ADC. . 45 3.31 Sampling timing diagram example. . . . . . . . . . . . . . . . 45 3.32 Magnitude and phase diagrams of the open-loop preamplifier transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.33 Step responses of the preamplifier stages for a LSBd''e differ- ential input. The blue trace represents the differential output

voltage of the first stage, while the red trace shows the differ-

ential output voltage of the second stage. . . . . . . . . . . . 48 3.34 Magnitude and phase diagrams of the loop gain transfer func- tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.35 Timing diagrams of the SAR control logic. . . . . . . . . . . . 52 3.36 Timing diagrams for the first three cycles of a conversion. . . 53 3.37 Timing diagrams of the cycles used to determine the last 9 bits of the digital output. . . . . . . . . . . . . . . . . . . . . 54 3.38 Successive approximation register for binary search. . . . . . 55 3.39 Chain of inverters to generate the delayed clock signal. . . . . 55 3.40 Floorplan of the SAR ADC. . . . . . . . . . . . . . . . . . . . 56 3.41 Analog and digital blocks composing the SAR ADC. . . . . . 57 3.42 Layout of the shared digital logic among all the ADCs on chip. 57

3.43 Floorplan of the ADCs integrated on the MEA chip. . . . . . 57 7 4.1 Example of an analog-to-digital conversion performed by the

SAR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 DNL histogram plot of the SAR ADC. . . . . . . . . . . . . . 59 4.3 INL histogram plot of the SAR ADC. . . . . . . . . . . . . . 60 4.4 2''048-points FFT output of the SAR ADC. . . . . . . . . . . 60 5.1 Switched-capacitor DAC equivalent circuit. . . . . . . . . . . 64 5.2 3-bit switched-capacitor DAC and its equivalent circuit. . . . 66 8 List of Tables 1.1 Performance summary of the MEA chip presented in [1]. The

reported values are based on experimental measurements. . . 5 2.1 Specifications for a single ADC. . . . . . . . . . . . . . . . . . 7 3.1 Summary of the most relevant parameters for the available

types of capacitors. . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Examples of the resulting parametric estimation of '(VM,D IN =256) for the bw and 2bw1Cs capacitive arrays. . . . . . . . . . . . 21 3.3 Summary of the results for the design of the capacitive array. 22 3.4 Calculated and simulated settling time for DIN transiting

from 0 to 256. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5 Preamplifier specifications. . . . . . . . . . . . . . . . . . . . . 47 4.1 Summary of the ADC power consumption. . . . . . . . . . . . 60 4.2 Requirements and estimated performance of a single SAR ADC. 61 4.3 Specifications of the single-slope data-conversion system cur-

rently implemented on chip, compared to the performance of

the SAR ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9 Abstract For both the electrical stimulation and recording of cultured neurons, the

CMOS-based microelectrode arrays (MEAs) are one of the most promising

electronic devices used nowadays. To ensure a robust transmission of the

information between the chip and external devices, the MEA chip requires

integrated analog-to-digital converters (ADCs). Moreover, the presence of a

large number of read-out channels on chip poses stringent requirements on

both area and power consumption for the design of the ADCs. Thus, this

Master''s thesis work proposes a low-power and compact successive approx-

imation register (SAR) ADC for such bio-electronic chips. In this thesis, some low-power ADC topologies are first investigated and the SAR ADC is finally chosen, that is the optimum solution for the ap-

plication. The choice of multiplexing the read-out channels of the MEA

chip for the analog-to-digital conversion is then presented while the require-

ments for the ADC are derived. In this work, the design of each part of the

converter is described, starting from the switched-capacitor array which is

usually used as a sample and hold (S/H) as well as a digital-to-analog con-

verter (DAC). The size of the switches that are providing the signals to the

DAC is optimized considering the timing requirements. Furthermore, low

power solutions are proposed for the comparator while good performances

are achieved for both noise and speed. A successive approximation register

logic is finally used to provide the digital control signals. The performance of the SAR ADC is evaluated with post-layout simula- tions. All the preliminary requirements are met and the proposed converter

represents a promising solution for low-power applications. In conclusion,

the specifications of the entire data-conversion system are compared with

the ADCs currently implemented on the MEA device and a possible im-

provement of the chip is presented. Key words: Microelectrode Array (MEA), Switched-Capacitor (SC) Suc-

cessive Approximation Register (SAR) Analog-to-Digital Converter (ADC),

Low-Power, Split Capacitor Array, Offset Cancellation. 10 Sommario Fra i dispositivi che permettono la stimolazione e la misura dell''attivit` a elettrica di colture neuronali, i CMOS microelectrode array (MEA) sono

una delle migliori soluzioni utilizzate oggigiorno. Per una sicura trasmissione

di informazioni dal chip ai dispositivi esterni, il dispositivo MEA richiede

convertitori analogico-digitali (ADC) da integrare nel chip. In particolare,

la progettazione di tali circuiti deve essere eseguita limitando il consumo di

area e potenza in quanto il numero di canali di lettura integrati ` e elevato. Per questo motivo, la presente tesi propone un ADC ad approssimazioni

successive (SAR) compatto e a basso consumo di potenza per chip bio-

elettronici. In questa tesi, diverse tipologie di ADC a risparmio di potenza sono in- izialmente investigate e il modello SAR ` e infine scelto, in quanto dimostra di essere la soluzione ottimale per l''applicazione studiata. La scelta di utilizzare

il multiplexing dei canali di lettura per la conversione analogico-digitale ` e quindi presentata assieme alle specifiche dell''ADC. La progettazione di ogni

componente elettronico del convertitore ` e poi descritta, iniziando dall''array a capacit` a commutate che ` e usato sia come sample and hold (S/H), sia come convertitore digitale-analogico (DAC). Le dimensioni degli interruttori che

forniscono i segnali al DAC sono ottimizzate considerando le specifiche del

tempo di assestamento. Una soluzione a basso consumo di potenza ` e pro- posta per il comparatore e un registro ad approssimazioni successive ` e usato per generare i segnali digitali di controllo. Le prestazioni dell''ADC SAR sono valutate con simulazioni post-layout. Tutte le specifiche stabilite sono soddisfatte e il convertitore proposto rap-

presenta una promettente soluzione per applicazioni a basso consumo di

potenza. La performance dell''intero sistema di ADC integrabile nel dispos-

itivo MEA ` e dunque confrontata con quella degli ADC a singola rampa al momento implementati sul chip e un possibile miglioramento del dispositivo ` e presentato. Parole chiave: Microelectrode Array (MEA), Convertitore Analogico-Digitale

(ADC) ad Approssimazioni Successive (SAR) a Capacit` a Commutate (SC), Basso Consumo di Potenza, Array a Capacit` a Commutate, Cancellazione dell''Offset. 11 Chapter 1 Introduction 1.1 Motivation The CMOS-based microelectrode arrays (MEAs) [1] are sophisticated de-

vices, which can be used to bidirectionally communicate with cultured neu-

rons. They can perform measurements at a high spatial and temporal resolu-

tion, which is hardly achievable with passive MEAs. A switch-matrix-based

high-density MEA chip [2] has been developed at Bio Engineering Labora-

tory of ETH Z¨ urich. With the switch-matrix scheme, an arbitrary subset of around 11''000 electrodes can be selected for recording and stimulation.

By placing the front-end amplifiers outside the array, a high signal-to-noise

ratio (SNR) has been achieved together with a subcellular spatial resolution. To ensure robust and stable transmissions of the information between the chip and other devices on the printed circuit board (Figure 1.1), the

amplified and filtered neural signals are usually digitized by on-chip analog-

to-digital converters (ADCs). The number of neural signals which can be

recorded simultaneously is limited by the number of read-out channels in-

tegrated on the chip, hence, in order to observe the electrical activity of a

large scale neural network, the 126 read-out channels of the previous design

are not sufficient. Therefore, the new version of the chip integrates much

more channels, posing stringent area and power consumption constraints on

the individual read-out channel and ADC. 1.2 MEA Chips Developed at BEL 1.2.1 Interfacing Electrogenetic Cells in Vitro with CMOS

Microelectrode Arrays Complementary semiconductor-metal-oxide (CMOS) technology is a very

powerful technology used to realize substrate-integrated microelectrode ar-

rays. These devices are arrangements of electrodes that can be more or 1 Figure 1.1: Packaged MEA chip on a custom-designed printed circuit board. less directly interfaced to electrogenetic cells, like heart or brain cells. It is

therefore possible to study fundamentals of learning processes and assess the

behavior of electrogenetic cells in vitro by culturing or placing them directly

atop the electronic chips, as shown in Figure 1.2. Figure 1.2: (a) Schematic of a cell attached to a sensor surface. (b) Micrograph of

an acute cerebellar brain slice (parasagittal cut) placed on a CMOS high-density electrode chip for measurements. The CMOS technology plays an important role for such devices since it allows the possibility to address a large number of microelectrodes on the

same chip, leading to a spatial sub-cellular resolution. Another advantage

of using CMOS integrated circuits (ICs) is the high signal quality provided

and the relative low-noise electrophysiological recordings that can be per-

formed from a variety of biological preparations. Many functions can be

programmed via software and digital interfaces. The recording technique is

extracellular and noninvasive, enabling long-term measurements. Applications areas for such devices include neuroscience as well as med- ical diagnostics and pharmacology. The most common biological prepara-

tions studied using microelectrode arrays are acute tissue preparations (e.g,

slices) which are recorded from immediately after they have been cut from 2 the animal and cell cultures. 1.2.2 The High-Density MEA Chip The Bio Engineering Laboratory (BEL) of ETH Z¨ urich designed a CMOS- based microelectrode array [1] featuring 11''011 metal electrodes and 126

read-out channels for extracellular bidirectional communication with elec-

trogenetic cells. The micrograph of the chip is shown in Figure 1.3. The

most important features include: ' High spatial resolution at (sub)cellular level with 3''150 electrodes per mm2. The electrode diameter is 7 µm and the electrode pitch is 18 µm. ' A reconfigurable routing of the recording sites to the 126 read-out channels. ' A low front-end input referred noise of 2.4 µVrms. Figure 1.3: Micrograph of the MEA chip (7.5 ' 6.1 mm2). The high-density arrays are usually CMOS-based devices that over- come the connectivity limitation by making use of on-chip signal multi-

plexing. The simultaneous recording from all electrodes requires the front-

end amplifiers being placed in each pixel (recording site), which, due to 3 area constraints, entails rather high noise levels. Instead of scanning the

entire electrode array, the approach of this device provides a reconfigurable

electrode/readout-channel routing to select an arbitrary subset of electrodes

for recording and stimulation. This enables both, low-noise signal record-

ing, and cellular or subcellular resolution, since the front-end circuitry can

be placed outside the array. Figure 1.4: Block diagram of the MEA chip. In the MEA chip designed by BEL [2] the read-out 126 channels and the associated signal amplification and stimulation circuitry are located outside

the reconfigurable electrode array, where sufficient area for a low-noise circuit

implementation is available (Figure 1.3). The readout channels includes two

amplification and filter stages. Both stages feature digitally configurable

gain and filter settings. The first stage provides bandpass filtering (BPF)

and a gain of 30 dB. The second stage provides an additional gain of either

0 dB, 20 dB or 30 dB with a second LPF. Eight channels are then multiplexed

and buffered by a third stage with an additional gain of 0 dB, 6 dB, 14 dB

or 20 dB, and finally digitized at 20 kHz using successive-approximation

analog-to-digital converters (ADCs) with a resolution of 8-bit. The digital

recording controller then transfers the data off chip by means of a 9-bit bus

together with chip-status information and a CRC (cyclic redundancy check)

for error detection. The chip was fabricated in an industrial 0.6 µm 3-metal 2-polysilicon CMOS-process. The total area of the device is 7.5 ' 6.1 mm2, while the

electrode array covers an area of 2.0 ' 1.75 mm2. The front-end input-

referred noise within the band of 1 Hz to 100 KHz is 2.4 µVrms. The maxi-

mum gain of the entire read-out circuit is 80 dB. The power consumption of

the front-end (first and second stage) is 160 µW/channel while the overall

power consumption of the chip is 135 mW. The most relevant specifications

characterizing the chip are summarized in Table 1.1. 4 Parameter Value Technology 0.6µm 3M2P CMOS Area 7.5 ' 6.1 mm2 Supply voltage analog 5.0 V Supply voltage digital 3.0 V Clock frequency recording controller 3.2 MHz Clock frequency comand controller 8 MHz Number of electrodes 11''011 Sensor area 2.0 ' 1.75 mm2 Electrode density 3''150 1/mm2 Power consumption overall 135 mW Power consumption front-end (stage 1&2) 160 µW/channel Front-end input-referred noise (1 Hz to 100 kHz) 2.4 µVrms Amplification 0-80 dB (18 steps) Table 1.1: Performance summary of the MEA chip presented in [1]. The reported values are based on experimental measurements. 1.3 Thesis Organization Requirements and specifications of the ADC for the new version of the MEA

chip are defined in Chapter 2 where different topologies of converters are an-

alyzed. Chapter 3 presents the design of the SAR ADC, showing the analysis

and simulations of the switched-capacitor array, switches, comparator and

SAR control logic. The characterization of the converter is shown in Chap-

ter 4 where the conclusions are reported. Finally, Chapter 5 is reserved for

the appendix. 5 Chapter 2 Specifications and ADC

Topologies This chapter provides the key design aspects for the new version of the chip.

The choice of multiplexing the read-out channels for the analog-to-digital

conversion is then presented and the requirements for the ADC are derived.

Finally, some low-power ADC topologies are investigated and the optimum

solution for our application is chosen. 2.1 Required ADC for the New Version of the

Chip The presence of on-chip ADCs is an essential requirement for allowing a

robust signal transmission between the chip and the printed-circuit board

(PCB). For the MEA chip presented in [2], 16 successive approximation

ADCs with a 8-bit resolution have been employed. In order to observe the electrical activity of a large-scale neural network, the new version of the chip needs to provide an increased number of channels

NChannels equal to 1''024, which poses stringent area and power consumption

constraints on the individual read-out channel and ADC. In order to improve

the signal quality, in the new design, the number of bits is increased to 10.

For this reason, a thorough noise and offset analyses of the converter are

key aspects that have to be considered during the design. 2.2 Elaboration of Specifications The frequency band for typical neural signals is roughly 10 Hz ' 5 KHz [3].

In order to avoid aliasing and ease spike sorting, the sampling frequency for

a single read-out channel is set to 20 KHz. The number of ADCs is reduced

by multiplexing the signals before their effective conversion. For the new 6 design, a number of 16 ADCs has been aimed to be integrated on the chip,

leading to the following sampling frequency fS for each converter: fS = NChannels NADCs fN = 1024 16 ' 20kHz = 1.28 M S/s (2.1) Due to limited chip area, the area for each ADC is restricted to 1 mm2. To reduce quantization error, 10-bit resolution is chosen while the signal-

to-noise and distortion ratio (SNDR) is set to be larger than 56 dB, which

corresponds to an effective number of bits (ENOB) equal to 9. The new

version of the chip will be designed using a 0.35 µm CMOS technology and

a 3.3 V power supply, aiming to a maximum power consumption of 1 mW

for each ADC. The preliminary specifications are summarized in Table 2.1. Parameter Value Resolution 10 bits Sampling rate 1.28 MS/s SNDR ' 56 dB Power consumption ' 1 mW Supply voltage 3.3 V Technology 0.35 µm CMOS Area ' 1 mm2 Table 2.1: Specifications for a single ADC. 2.3 Low Power ADC Topologies Overview In order to evaluate to evaluate which ADC architecture [4] best satisfies the

presented requirements, some of the most important topologies are briefly

reviewed in this section. Integrating ADC The Integrating ADC can be an appropriate solution for low-speed appli-

cations where low power consumptions are required. A possible implemen-

tation of this topology is the single-slope architecture, shown in Figure 2.1,

where the input signal is compared with a voltage ramp. Counting the time

required by the ramp to reach the signal value, it is possible to perform

the analog-to-digital conversion. Even if this solution presents a very sim-

ple structure (a comparator, the voltage ramp generator and the counter

in principle), it suffers from several drawbacks. A stable and precise ramp

generator is required since voltage and temperature coefficients can affect 7 the linearity of the conversion. Moreover, a high clock frequency is desired

in order to reach a sufficient resolution. Figure 2.1: Single-slope ADC [4]. Successive-Approximation ADC The successive-approximation ADC is based on the binary search algorithm

and it requires a simple structure based on a sample and hold (S/H), com-

parator, digital-to-analog converter (DAC) and the successive approxima-

tion register (SAR). This is a topology mostly used to design medium-high

resolution ADCs for medium-low speed applications. The DAC is controlled

by the SAR logic and its output voltage varies depending on the decision of

the comparator, as shown in Figure 2.2. Besides the simple structure, the

converter presents a low power consumption as well. Sigma-Delta ADC The Sigma-Delta ADC is one of the best solutions if high resolution is re-

quired in low frequency applications. The converter is based on the oversam-

pling and noise shaping techniques and it can achieve high signal-to-noise

ratio (SNR). The analog part of the circuit is simple since only a compara-

tor, voltage reference, integrators and analog summing circuits are required.

On the other hand, the digital circuitry is quite complex and it consists of

a digital signal processor (DSP) which acts as a digital filter and decimator

(Figure 2.3). The delta modulation is used to achieve higher transmission

efficiency by transmitting the changes (delta) in value between consecutive

samples. Combining the oversampling with the sigma-delta modulator it 8 Figure 2.2: Successive-approximation ADC structure [4] and a 4-bit analog-to- digital conversion. is possible to obtain a high SNR at low frequencies by shaping the quanti-

zation noise such that most of it occurs outside the bandwidth of interest.

The noise outside the frequency bandwidth of interest will be removed by

the digital filter while the decimator will reduce the output data rate back

to the Nyquist rate. Some of the disadvantages of this structure are the high

clock frequency required and the large silicon area consumed by the digital

part. Figure 2.3: First-order sigma-delta ADC [4] 9 2.4 Fully Differential Switched-Capacitor SAR ADC Considering the ADC specifications mentioned in Section 2.2, the successive

approximation ADC has been preferred among the three different low-power

ADC topologies presented. The most relevant advantages of this topology

are the following: ' Low power consumption: Since the SAR ADC does not contain any power-hungry operational amplifiers (OpAmps), it is a well-known

topology for its power efficiency. In fact, the comparator usually con-

sumes less than an OpAmp since it does not need linear settling. ' Simple structure: The low complexity of the circuit ease its imple- mentation on chips where compact realizations are required. This is

also due to the very simple principle on which the ADC is based, the

binary search algorithm. Moreover, promising solutions can also be

evaluated in order to reduce even more the total area required by the

ADC. In particular, the converter presented in this work is a fully differen- tial switched-capacitor or charge-redistribution SAR ADC [5]. This circuit

incorporates an array of capacitors that is usually used as a S/H as well

as a DAC. In order to better understand the operation, we first consider a

simple single-ended 3-bit switched-capacitor ADC with a binary weighted

capacitive array [6], which is shown in Figure 2.4. The main parts of the

circuit are: the capacitive array, the switches, the comparator and the SAR

control logic. Figure 2.4: 3-bit single-ended switched-capacitor SAR ADC. During the sampling phase, the top plates of the capacitors are reset to the common voltage VCM while all the bottom plates of the capacitors are

connected to the input signal source Vsig that is equal to the sum of VCM

and the input signal component ''Vsig. The switches resetting the input

node of the comparator are then turned off and all the bottom plate nodes

are connected to VCM , performing the so-called ''bottom plate sampling'' [7].

Now that the voltage VCM '' ''Vsig is stored on the top plate node of the 10 capacitors, the switch controlled by D2 is connected to VREF and a voltage

equal to VREF /2 is added to VCM '' ''Vsig. The comparator can therefore

determine the most significant bit (MSB) by comparing this value with VCM .

The SAR control logic either leaves the switch controlled by D2 connected

to VREF or connects it back to VCM depending on the comparator output.

A similar process is followed for the remaining two bits leading to the deter-

mination of the digital output value. All the switches are then reset again

to the initial positions and the converter can start another cycle of conver-

sion [4]. Note that the extra LSB capacitor (C in the case of the 3-bit DAC)

is required to make the total value of the capacitive array equal to 8C, so

that binary division is accomplished when the individual bit capacitors are

manipulated. Using the same switched-capacitor array of the previous example and considering a fully differential topology of the circuit, the 4-bit ADC shown

in Figure 2.5 is obtained. This new structure differs from the single-ended

one in Figure 2.4 in various aspects, i. e., the differential input signal for

the comparator, two identical capacitive arrays and two different references

voltages VREF P and VREF N . Note that this structure gains an additional bit

D3 that is the ''sign bit'' and it is determined once the differential input signals

are sampled on the input nodes of the comparator. Hence, the MSB bit

corresponds to the sign of the output digital value. Each reference voltage is

assigned to a capacitive array depending on the result of the sign bit decision.

At this point, the switch controlled by D2 in each array is connected to

the respective reference voltage and the values of the remaining 3 bits are

determined using the binary search algorithm, as explained in the single-

ended example. The voltages at the input nodes of the comparator, VipA and

VinA, during the sampling and conversion phases are shown in Figure 2.6. Figure 2.5: 4-bit fully differential switched-capacitor SAR ADC. 11 Figure 2.6: Voltages at VipA and VinA during the sampling and conversion phases for the 4-bit fully differential switched-capacitor SAR ADC [8]. Since the overall accuracy and linearity of the SAR ADC is primarily determined by the internal DAC, the switched-capacitor realizations of it

have become very popular in newer SAR ADCs due to their high accuracy

and linearity. A high degree of temperature stability is another advantage

of these capacitive DACs. Moreover, the fully differential analog signal path has been preferred respect to a single-ended one for the following main

reasons: ' Immunity to common-mode noise. ' The input dynamic range is doubled, which relaxes the design require- ments of the comparator. 12 Chapter 3 Design implementation 3.1 Design Guidelines The design of the SAR ADC has been conducted focusing on the power

and area constraints while maintaining good linearity performances for the

analog-to-digital conversion. Switched-capacitor arrays are used to imple-

ment both the S/H and DAC while minimizing the area of the unit capac-

itor. Parasitic capacitances and matching properties have been taken into

account during the analysis. Switches are providing the signals to the DAC

and their size has been optimized focusing on the timing requirements. A

low power solution is proposed for the comparator while achieving good noise

performances and speed requirements. The input-offset storage technique

has been chosen for this stage and a dynamic latch has been preferred. The

digital control signals are provided by a successive approximation register. 3.2 Switched-Capacitor Array The design of the switched-capacitor array is a key aspect for the overall

performance of the entire SAR ADC. Generally, the array is used as: ' S/H : the differential input voltage can be stored at the input nodes of the comparator using the bottom plate sampling technique [7]. ' DAC : in combination with the SAR control logic, the switched-capacitor array can provide the required voltage variations to perform the binary

search. Usually the capacitive array is the part of the circuit that requires the largest

silicon area due to a large number of capacitors. Different design solutions

can be taken into account to reduce the size of the array while maintaining a

good linearity performance for both S/H and DAC. In particular, the struc-

ture of the array can be modified and the unit capacitor can be minimized. 13 However, these design choices can lead to larger parasitic capacitances and

worse matching. For this reason, an accurate and precise analysis is required

in order to choose the best solution. The analysis should cover also the choice of the type of capacitor. The available technology offered two main types: poly-poly (cpp) capacitors and

metal-metal (cmm) capacitors. The most relevant parameters describing

these topologies in terms of capacitance, bottom plate parasitic capacitance

and matching parameters are summarized in Table 3.1. cpp capacitor cmm capacitor Area capacitance 0.85 fF/µm2 1.25 fF/µm2 Perimeter capacitance 0.021 fF/µm 0.111 fF/µm Parasitic area capacitance 105 aF/µm2 12 aF/µm2 Parasitic perimeter capacitance 57 aF/µm 36 aF/µm Minimum area 17.24 µm2 25 µm2 Minimum unit capacitance 15 fF 33.47 fF Matching parameter AC 1.25% µm 0.65% µm Table 3.1: Summary of the most relevant parameters for the available types of capacitors. The capacitor matching is described by the following equation: ' ''C C = AC '' W L (3.1) where ' ''C C is the standard deviation of the difference ''C of identically designed capacitors, normalized to their absolute value C. The parameters

W and L define the geometric size of the capacitor. Since the MSB is the sign bit, two identical 9-bit capacitive arrays are required for the SAR ADC. Most of the analyses have been conducted con-

sidering only one capacitive array, extending then the results to the differ-

ential case. For this reason, it is better to differentiate the least significant

bit (LSB) definition in the two following cases: ' Differential signal path: the required resolution n of the ADC is 10 bits for a differential dynamic input range of F Sd''e = 4V . The input

signal for the ADC is in fact differential and each single-ended signal

has a range of 2V. This results in a differential LSBd''e equal to: LSBd''e = F Sd''e 2n = 4V 210 '' 3.906 mV (3.2) ' Single-ended signal path: since the switched-capacitor DAC is con- trolled by a 9-bit digital input signal DIN , it is possible to define 14 the single-ended LSBs''e. This value is useful to evaluate the perfor-

mance of each DAC and then estimate the differential performance

while adding linearly this error, which represents the worst case. LSBs''e = VREF P '' VCM 29 = 1V 29 '' 1.953 mV (3.3) Note that, depending on the sign bit, the analog input range of the single-

ended signals becomes either [1.65 , 2.65] V or [0.65 , 1.65] V. However, the

value of the single-ended full scale range F Ss''e is equal to 2 V, as expected. Split Capacitive Array The most popular switched capacitor DAC is an array of parallel binary-

weighted capacitors [6]. The structure is shown in Figure 3.1 for a 9-bit

DAC where the capacitor C is equal to the unit capacitor chosen. After

being discharged, the bottom plates of the capacitors are connected either

to a reference voltage or to VCM , determining an output voltage Vm which

is a function of the voltage division between the capacitors. The equivalent

circuit of the DAC is shown in Figure 3.2. Considering m as the number

of capacitors connected to the reference voltage VREF P , the equation giving

the value of Vm is the following: Vm = VCM + (VREF P '' VCM ) m 29 (3.4) Figure 3.1: Binary weighted switched-capacitor array. As a drawback, the presented capacitive array requires a large area due to the large number of capacitors. The total capacitance of the array is in fact

29C, which can result also in a large dynamic power consumption. A possible

solution that can be considered is splitting the array in parts using one or

more series capacitors [6]. Maintaining the binary weighted capacitor size

for the sub-arrays and choosing the correct values for the series capacitors, it

is possible to maintain the same ratios for the voltage division, obtaining the

identical equation given in (3.4). For the 9-bit switched capacitor DAC, the

array can be split in two parts (2bw1Cs array), five parts (5bw4Cs array) or

it can be even realized with a C-2C ladder (C2C array) [9]. These topologies

are shown in Figures 3.3, 3.4 and 3.5 where the total capacitance is in fact 15 Figure 3.2: Binary weighted switched-capacitor array equivalent circuit. Figure 3.3: 2bw1Cs capacitive array. Figure 3.4: 5bw4Cs capacitive array. Figure 3.5: C2C capacitive array. reduced (e.g., the 2bw1Cs presents a total capacitance of approximately

48.07C).

However, the series capacitors introduce bottom-plate parasitic capacitances

that are affecting the top-plate nodes of the sub-arrays, hence decreasing the

linearity of the ADC. In addition, the matching is also degraded due to the 16 capacitors whose value is a fraction of the unit capacitor, such as 16

15 C and 4

3 C . An accurate analysis of these effects is therefore required in order to choose a split capacitive array that provides the required linearity and

matching for the DAC, while occupies the smallest chip area. 3.2.1 Capacitive Array Design Thermal Noise (kTC Noise) The first limiting factor for the minimum acceptable size of the capacitors

is the Johnson-Nyquist noise (thermal noise) that is usually referred as kTC

noise for the sampling circuits [6]. Considering that the entire ADC has two

capacitive arrays, the mean-square value expressing the thermal noise for

each array is summed up while considering the SNR of the entire structure.

Since the two arrays are identical, the worst SNR due to the kTC noise can

be written as follows: SN RT hermal = PSignal PT hermal = 10log10

1 2 F Sd''e 2 2 2 kBT Cu

(3.5) where kB is the Boltzmann constant, T is the temperature expressed in

Kelvin and Cu is unit capacitor considered. Since for all the different split

capacitive array topologies there is always a unit capacitor connected to the

output node of the DAC, this capacitive value has been considered for the

calculation as worst case. Comparing this SNR with the theoretical signal-

to-quantization-noise-ratio (SNQR) of the ADC, it is possible to find a value

of the capacitor Cu that returns a negligible kTC noise. The definition of

the SQNR is the following: SQN R = 10log10

1 2 F Sd''e 2 2 LSBd''e 12

= 6.02n + 1.76 (3.6) For a 10-bit ADC, the theoretical SQNR is equal to 62 dB. The value of the

unit capacitor is therefore found considering the following condition: SN RT hermal ' SQN R (3.7) That results in the a minimum capacitor values at a temperature T of 300 K

equal to: Cu ' 10 6.02n+1.76 10 ' 4kBT 2 F Sd''e 2 '' 6.55 f F (3.8) Being 15 fF and 33.47 fF respectively the minimum unit capacitance Ccpp,min

and Ccmm,min for the technology considered (Table 3.1), the effect of the kTC

noise is not relevant and it can be neglected in the future considerations. 17 Parasitic Capacitances Every integrated capacitor presents parasitic capacitances between its plates

and the surrounding layers. This parasitics can be therefore summarized in

two groups: top-plate (TP) parasitic capacitances and bottom-plate (BP)

parasitic capacitances, depending on which plate is considered. Since usually

the BP parasitic capacitances presents the highest value, the effect of the

TP parasitic capacitances has been neglected during the presented analysis.

Considering first the bw capacitive array (Figure 3.1), the BP nodes of all

the capacitors are always connected to a fixed voltage value (either to a

reference voltage or VCM ), hence the parasitic capacitances are not affecting

the DAC characteristic of the output voltage. This is not true for the split

arrays where the series capacitors are adding parasitics on the TP nodes of

the sub-arrays, giving a gain error and decreasing the linearity of the DAC.

As an example, the 2bw1Cs capacitive array is shown in Figure 3.6 where

the BP parasitic capacitance Cp1 of the series capacitor Cs1 has been added.

Note that Cp1 is considered to be connected between the top-plate of the

LSB sub-array and the n-well where the capacitive array is placed. This

well is tied to VDD. Figure 3.6: 2bw1Cs switched-capacitor array with the bottom-plate parasitic ca- pacitance added. Both effects can be highlighted in the equation of the output voltage of the

DAC, which is obtained by solving the system of equations given by the

charge conservation principle. Considering the 2bw1Cs capacitive array as

an example, the equivalent circuit of the DAC is shown in Figure 3.7 where

m and p are the sums of the unit capacitors connected in parallel to the

reference voltage in the LSB sub-array (C6''9) and MSB sub-array (C1''5)

respectively. The values of m and p depend on the digital input DIN of the

DAC, for example: if DIN = 256 = 100...0, then m = 0 and p = 16.

Assuming that all the capacitors are discharged before applying the digital

input signal, the equations given by the charge conservation principle are

the following: Cp1(VCM '' VDD) = mC(VL '' VREF P ) + (16 '' m)C(VL '' VCM ) + + 16 15 C(VL '' VM ) + Cp1(VL '' VDD) 18 Figure 3.7: 2bw1Cs switched-capacitor array equivalent circuit. 0 = pC(VM '' VREF P ) + (31 '' p)C(VM '' VCM ) + 16 15 C(VM '' VL) (3.9) Solving the previous system of equations, the output voltage VM of the DAC

is: VM = VCM +(VREF P ''VCM ) 16(m + 16p)C 8192C + 481Cp1 + 15pCp1 8192C + 481Cp1 (3.10) While not considering the parasitic capacitance (Cp1 = 0) the equation is

reduced to the output voltage equation of an ideal 9-bit DAC: VM = VCM + (VREF P '' VCM ) m + 16p 512 (3.11) Comparing (3.10) with (3.11) it is therefore possible to note how the parasitic

capacitance Cp1 is affecting both gain error and linearity. Focusing on the linearity of the DAC, the integral nonlinearity (INL) graph can be estimated for each presented topology. This can be done by solving the equations given by the charge conservation principle while

considering the BP parasitic capacitances, finding the equation of the output

voltage and proceeding then with the INL estimation. The INL values have

been found comparing the effective output voltage with its best fitting line

in order to eliminate the gain error [4]. As an example, the estimated INL

graph for each split capacitive array topology is shown in Figure 3.8 where

minimum-size cmm capacitors have been used. The binary weighted solution

has not been considered since no BP parasitic capacitances are connected

to the TP node of the array. Note that each graph has been found while

considering only one capacitive array, hence the LSB considered is referred

to the single-ended case, that has been estimated in (3.3). The results can

be extended to the differential case since both capacitive arrays in the ADC 19 are identical. From the INL results shown in Figure 3.8, it is possible to

notice that the more the array is divided into parts, the more it is affected

by the parasitic components. Hence, the area of the unit capacitor should

be increased in order to reduce the parasitic capacitances and limit this

effect. The tradeoff between the linearity and required area will be therefore

considered while comparing all the results, aiming the following requirement: IN L ' 0.5LSBs''e (3.12) Figure 3.8: INL graph estimation of each split capacitive array. Matching of the Capacitors The matching of the capacitors is another key aspect that has to be taken

into account in order to achieve a desired performance from the capaci-

tive DAC. The matching properties of capacitors depend on the technology

used, the capacitor size and the layout employed. While for the layout design a common-centroid technique has been considered (Section 3.6), in

this section, a pre-layout estimation of the capacitors matching has been

studied [10]. The output voltage of each 9-bit DAC for the half-range dig-

ital input code (DIN = 256 = 100...0) presents the worst case in terms of

mismatch among the capacitors [11], hence the standard deviation of this

voltage should be constrained with the following condition: 3'(VM,D IN =256) ' 0.5LS Bs''e (3.13) 20 where VM,D IN =256 is the output voltage value for the half-range digital input code and is ideally equal to: VM,D IN =256 = VC M + VREF P '' VCM 2 = 2.15 V (3.14) If (3.13) is satisfied, the linearity performance of the DAC is met. Note that

if the requirement is met considering only one capacitive array, the result

can be extended also for the differential case. Considering the parametric

expression of the output voltage of the DAC and assuming that the mis-

match of each capacitor is independent, it is possible to estimate both the

mean value and the standard deviation of '(VM,D IN =256). The calculations have been conducted using the properties of the variance from the statis-

tics theory. A simplified example of this type of calculation is reported in

Appendix 5.2 for a 3-bit capacitive DAC. This type of estimation has been

conducted for each capacitive array topology presented before. The values of

'(VM,D IN =256) for both the bw and 2bw1Cs capacitive array are presented in Table 3.2, where µC is the mean value of the unit capacitor considering

both area and perimeter capacitance (Table 3.1) and 'C is the standard

deviation of the unit capacitor, that is defined as follows: 'C = ' δC C µC = ' ''C C '' 2 µC (3.15) Capacitive array topology '(VM,D IN =256) bw (VREF P '' VCM ) '' 3'C 32 '' 2µC 2bw1Cs (VREF P '' VCM ) 'C q 24591µ2 C + 15' 2 C 1024µ2 C Table 3.2: Examples of the resulting parametric estimation of '(VM,D IN =256 ) for the bw and 2bw1Cs capacitive arrays. Since both µC and 'C depend on the area of the unit capacitor, by substi-

tuting the parametric expressions in (3.13), one can determine the minimum

unit capacitor area that satisfies the condition. The results found with the

analytical method have been compared with MATLAB simulations where

the '(VM,D IN =256) value has been calculated considering the capacitor vari- ables as 100-points gaussian distributions. The comparison shows that the

proposed method overestimates the minimum unit capacitor area and this is

probably due to the independent-variables assumption. However, this type

of analysis can still be used to roughly determine the unit capacitance with

some margin. 21 Results and Considerations Summarizing all the results found in the previous analyses, one can decide

the capacitive array topology, the type of capacitor and its unit area that

best fit for our application. Since the kTC noise can be considered negligi-

ble, the minimum unit capacitor area W L that satisfies both the parasitic

capacitance (PC) condition (3.12) and the capacitive matching (CM) con-

dition (3.13) are summarized in Table 3.3. PC CM Overall WL [µm2] WL [µm2] WL [µm2] # Cu CT ot [fF] bw cpp min min min 512 7''682 cmm min min min 512 17''137 2bw1Cs cpp 17.28 min 17.28 48.07 722 cmm min min min 48.07 1609 5bw4Cs cpp 140.63 >1''000 >1''000 - - cmm 38.03 105 105 20.50 2''784 C2C cpp 248.27 >1''000 >1''000 - - cmm 74.95 >1''000 >1''000 - - Table 3.3: Summary of the results for the design of the capacitive array. The total number of unit capacitors required in the array is # Cu and CT ot is

the total capacitance of the array. The min value states that the minimum-

size unit capacitor satisfies the considered design condition. On the other

hand, when a unit capacitance area less than 1''000 µm2 cannot satisfy the

matching condition for a certain condition, the topology is discarded. As

expected, it is possible to notice how the split topologies are affected by

both parasitics and mismatch. In particular, the 5bw1Cs and C2C can be

discarded since they require a very large unit capacitor mostly due to the

presence of BP parasitic capacitances. Hence, the 2bw1Cs capacitive array

has been chosen since it meets the requirements with the minimum unit

capacitance value. Furthermore, cmm capacitors have been preferred due

to their better matching characteristic and less parasitic capacitances. Split Capacitive Array Realization The 2bw1Cs capacitive array chosen includes a series capacitor Cs1 with a

value of 16

15 C whose layout design could be cumbersome. In addition, its matching properties could be worse than those of the other capacitors since 22 its capacitance is not an integer multiple of the unit capacitor C. Therefore,

the modified split capacitive array presented in [13] has been adopted in this

work. The modified array, shown in Figure 3.9, differs from the common

2bw1Cs structure for the following two aspects: ' The series capacitor is substituted with a unit capacitor, i. e., Cs1 is equal to C. ' The additional parallel capacitor Ce of the LSB sub-array is removed. Figure 3.9: Modified split capacitive array. In order to check the accuracy of the proposed solution, it is possible to study the equivalent circuit of the DAC, which is shown in Figure 3.10.

Assuming that all the capacitors are discharged before applying the digital

input signal and neglecting the effect of the parasitic capacitance (Cp1 = 0),

the equations given by the charge conservation principle are the following: 0 = mC(VL '' VREF P ) + (15 '' m)C(VL '' VCM ) + C(VL '' VM )

0 = pC(VM '' VREF P ) + (31 '' p)C(VM '' VCM ) + C(VM '' VL) (3.16) Figure 3.10: Modified split capacitive array equivalent circuit. Solving the previous system of equations, the output voltage VM of the DAC

is found as follows: 23 VM = VCM + (VREF P '' VCM ) m + 16p 511 (3.17) Comparing (3.11) with (3.17), it can be noticed that a gain error of 1 LSB

introduced by the proposed array. However, this is not severe since the

gain error caused by the input capacitance of the comparator is even larger

(Appendix 5.1). DAC Post-Layout Simulations on Cadence The reliability of the previous analyses can be verified by simulating the

DAC with Cadence. First of all, the linearity of the DAC is evaluated by

running an INL analysis which, however, takes into account only the effects

of the parasitic capacitances. The results given by the pre-layout simulations

match the previous estimated values. Nevertheless, the performance of the

DAC decreases while checking the post-layout simulations. This is due to

the two following aspects: ' The parameters describing the different capacitor technologies (Ta- ble 3.1) are defined as mean values. The minimum unit capacitance

can be considered as a boundary case, hence the estimations could be

not accurate enough. ' The post-layout simulations take into account the coupling effects be- tween the capacitors and wires, that are difficult to estimate. This

aspect can be critical since the unit capacitance could be comparable

to the parasitic and wiring capacitances. For this reason, the layout design of the capacitive array has been conducted

in order to reduce the parasitic effects and maximize the DAC performance.

The common-centroid technique [15] has been chosen to reduce the com-

plexity of the structure and, hence, minimize the wiring. In addition, while

the metal layers MET2 and MET3 have been reserved for the capacitors

and the internal connections, MET1 has been used to wire the input signals

and to reduce capacitive unbalances of the structure due to the asymmetric

structure. The capacitive array floorplan is shown in Figure 3.11 where Csd

is the dummy capacitor of Cs1.

The modified split capacitive array implemented with minimum unit capac-

itors (Cu=33.47 fF) manifests an INL that is always less than 0.5 LSBs''e.

However, the unit capacitor Cu has been finally increased to 64.36 fF in

order to have some margin on the performance. The INL graphs of both

cases are shown in Figure 3.12. The DAC non-linearity caused by the capacitance mismatch has been verified with a 1''000-runs Monte Carlo simulation. The worst-case value of

VM,D IN =256 has been considered and measured. The following results have been obtained: 24 Figure 3.11: Floorplan of the capacitive array. Figure 3.12: INL graphs of the 9-bit DAC comparing two different values for the unit capacitance. 25 ' µ(VM,D IN =256) = 2.150 V ' '(VM,D IN =256) = 82.30 µV It is possible to compare the standard deviation of VM,D IN =256 with the 0.5 LSBs''e reference value as follows: 3'(VM,D IN =256) = 246.90 µV 0.5 LSBs''e '' 1.953 mV (3.18) Hence, the estimations about the DAC non-linearity are reliable. Dynamic Power Consumption The dynamic power consumed in the array can be estimated considering

both the power required by the DAC and the power delivered during the

sampling phase [14]. Considering only one capacitive array, it is possible to

estimate these values as follows: PDAC = fS 9 X i=1 Ei '' fSCChargedV 2 REF (3.19) PSamp = fSESamp = fSCCharged F Ss''e 2 2 (3.20) where fS is the sampling frequency which is equal to 1.28 MS/s, Ei the

energy required by the DAC for the i-th digital input applied, CCharged is

the total capacitance charged during the DAC phases (note that the voltage

across the series capacitor is assumed to remain the same) and is equal to

46C, VREF is the voltage at which each capacitor is charged and is equal to

1 V and ESamp is the energy required by the sampling phase. Considering

both capacitive arrays, their total dynamic consumption is therefore the

following: PT ot = 2(PDAC + PSamp) '' 2fSCCharged " V 2 REF + F Ss''e 2 2 # (3.21) Which results in a total power consumption PT ot equal to 15.16 µW. Since

the total power required to charge the array is proportional to CCharged, it

is favorable to split the array. For a conventional binary weighted array, the

equivalent charged capacitance is 512C which leads to a PT ot of 168.72 µW

for the same unit capacitance. The previous estimated values can be verified by a simple simulation on Cadence. Considering first the DAC phase, the switching behavior can

be simplified in two steps: while the top-plate nodes of both MSB and

LSB sub-arrays are first maintained at VCM , the bottom-plate nodes of

all capacitors excluding Cs1 are switched between VREF P and VCM . The 26 switching frequency of this circuit has to be equal to 1.28MS/s that is the

sampling frequency fS. Hence, the power consumed by the DAC can be

estimated as follows: PDAC,Sim '' (VREF P '' VCM )IAvg (3.22) where IAvg is the average current delivered by the reference voltage source

calculated on 1''000 cycles. For the sampling phase, the switching behavior

is the same and, instead of VREF P , the maximum input voltage value is

applied. Since this value is theoretically equal to 2.65V, that is actually

VREF P , both the circuit and the conditions are exactly equal to the previous

case. Hence, PSamp,Sim is equal to PDAC,Sim, as obtained also in the previous

calculations. The total dynamic consumption estimated before is verified by

this simulation, as it can be noticed from the results: PT ot,Sim = PDAC,Sim + PSamp,Sim '' 2(VREF P '' VCM )IAvg = 15.59 µW (3.23) 3.3 Switches Each capacitive array requires a relatively high number of switches that are

used both for passing signals and reset the voltage values at specific nodes.

A design analysis based on the settling time and sampling linearity has been

conducted in order to optimize the size of each switch. 3.3.1 Switch Structures The switched-capacitor array is used both for sampling the input signal and

providing comparing reference voltages required by the SAR algorithm. In-

put and reference signals are applied to the bottom-plate of the capacitors

using switches. On the other hand, the top-plates of the capacitors belong-

ing to the LSB sub-array are reset by applying the common-mode voltage

VCM through only one switch (Figure 3.13) while the node VM is reset by

the preamplifier stage during the offset-cancellation phase, as shown in Sec-

tion 3.4. For this reason, the switches used can be divided into two groups: ' Bottom-plate switches: they pass the input voltage signal, the common voltage or one of the two reference voltages to the bottom-plate of the

capacitors. ' Top-plate switch: it resets the voltage value at the VL node passing the common voltage. The structure of the entire capacitive array with the switches is shown in

Figure 3.13 where VBP can be one of the four voltages mentioned before and

here summarized with their voltage values or range: 27 ' 0.65 V ' VSig ' 2.65 V ' VCM = 1.65 V ' VREF P = VCM + VREF = 1.65 V + 1 V = 2.65 V ' VREF N = VCM '' VREF = 1.65 V '' 1 V = 0.65 V Figure 3.13: Capacitive array with ideal bottom-plate and top-plate switches. Starting first the design of the BP switches, they can be organized choos- ing one of the following main structures: ' Mux-like (ML) structure: four different switches are connected to the bottom plate of each capacitor in the array, respectively passing the

voltages VSig, VREF P , VREF N and VCM . Figure 3.14 shows the struc-

ture connected to the bottom plate of one capacitor. ' Shared-block (SB) structure: the bottom plate of each capacitor is di- rectly connected to two switches only. While one switch is passing

VCM , the other is connected to a structure shared among all the ca-

pacitors belonging to the array. This structure is made up of three

switches that are providing the remaining voltages (VSig, VREF P and

VREF N ). This topology is shown in Figure 3.15 where the shared block

has been highlighted. The SB structure has been implemented because it requires a less compli-

cated control logic and routing due to the shared structure. Although the

switches are connected in series, this solution does not need very low switch

on-resistance. Still good performances can be achieved while maintaining

small gate-width and minimum gate-length for all the transistors used. Only NMOS pass-transistors (NMOS PTs) have been used to implement the switches passing the negative reference voltage VREF N and common

voltage VCM while PMOS pass-transistors (PMOS PTs) are used to provide

the highest reference voltage VREF P . On the other hand, transmission-

gates (TGs) are preferred while passing the input voltage, whose range is

from 0.65 V to 2.65 V. Considering the SB structure, the switch T GBP that

controls the passage of VSig, VREF P and VREF N for each capacitor is also a 28 Figure 3.14: Mux-like structure for the switches of the capacitive array. Figure 3.15: Shared-block structure for the switches of the capacitive array. transmission-gate. The on-resistance values of both NMOS PT and PMOS

PT depend on the input signal VSig and their definitions are shown in (3.24)

and (3.25) respectively [12]. Ron,N = 1 µnCox W L N (VDD '' VSig '' VT N ) (3.24) Ron,P = 1 µnCox W L P (VSig '' |VT P |) (3.25) 29 where Cox is the MOS gate capacitance per unit area, W L the aspect ratio and VT the threshold voltage. Since the electron mobility µn of the NMOS

transistors is approximately three times larger than the hole mobility µp of

the PMOS transistors for our technology, a scaled value of the minimum

gate-width can be used while sizing the PMOS switches. Hence, assigning

WP for the gate-width of the PMOS transistor and WN the gate-width of

the NMOS transistor, the relation between them is expressed as follows: WP = 3WN (3.26) Therefore, following the relation given by (3.26) and minimum gate-length

for the design of all the PTs, it is possible to reach a low on-resistance

value for the PMOS PTs that is comparable to the one of the minimum-

size NMOS switches for the respective input voltage ranges. Using the same design choice for the design of the transmission-gates, the variation

of its on-resistance as a function of the input voltage will be much less

compared to that of a pass-transistor. This result is shown in Figure 3.16

where this function has been plotted considering different values for WN

and maintaining the ratio given by (3.26). Finally, as a reference value, the

minimum size and aspect ratio for the gate of the NMOS transistors of the

switches provided by the technology used in this thesis are the following: W L N,min = Wmin Lmin = 0.7 µm 0.35 µm = 2 1 (3.27) 3.3.2 DAC Settling Time Most of the switches has been sized considering the settling time require-

ment of the DAC. During the settling phase, all the BP switches are in-

volved except for the shared transmission-gate that is directly passing the

input signal. It is therefore useful to study the RC equivalent model of

the switched-capacitor array where the switches are represented with their

on-resistance. The settling time of the output voltage provided by the 9-bit DAC reaches its largest value when the digital input is switched from DIN = 0

to DIN = 256, since the voltage difference between the initial and the fi-

nal value presents its maximum value which is ''V '' VREF 2 = 0.5 V . For the digital input value DIN = 256, the bottom plate of the capacitor C1 is

therefore connected to the series of the switches composed by T GBP and

one pass-transistor (NMOS or PMOS depending on the reference voltage)

while the bottom-plate of each other capacitor is connected to VCM through

the NMOS switch. Note, at this moment the TP reset switch is turned off.

The equivalent RC model is shown in Figure 3.17. In order to obtain a rough estimation of the settling time, it is gener- ally common to use the Open Circuit Time Constant (OCTC) analysis that 30 Figure 3.16: Dependance of the on-resistance value of the transmission-gate on the

input voltage value. While maintaing the relation (3.26), the value of WN has been swept from 0.7 µm to 7 µm. can be used to estimate the dominant time constant of the network. Un-

fortunately, in the case studied, this method is not accurate because there

are several poles having comparable frequencies. For this reason, another

approach has been used considering the following assumptions: ' For the LSB sub-array in Figure 3.17, each branch has a time constant whose value is comparable with the others. Hence, as an assumption,

the voltage at the bottom-plate of each capacitor connected to the

pass-transistor providing VCM is considered to be equal during the

transition. Therefore, these nodes can be shorted in the equivalent

circuit and the equivalent impedance of the LSB sub-array will be: ZBP,C s1 '' 1 15sC + RP T,V cm 4 (3.28) The impedance seen from the top-plate of the splitting capacitor Cs1

to VCM is approximately the following: ZT P,C s1 = 1 sC + ZBP,C s1 '' 1 sC + RP T,V cm 4 (3.29) 31 Figure 3.17: Equivalent RC model of the 9-bit DAC for DIN = 256. The resulting equivalent circuit is shown in Figure 3.18. ' At this point, the same assumption can be made once again since the time constants of each branch are still comparable. The bottom-plate

nodes of each capacitor connected to the pass-transistor providing VCM

are shorted together and the final equivalent model is shown in Fig-

ure 3.19. Figure 3.18: Simplified equivalent RC model of the 9-bit DAC for DIN = 256. 32 Figure 3.19: First-order equivalent RC model of the 9-bit DAC for DIN = 256. Now the equivalent model corresponds to a simple first order RC network

and the settling time can be easily estimated. Considering VREF P as refer-

ence voltage, the step response of the voltage node VM is described by the

following expression: VM (t) = VM 0 + VCM + VREF P '' VCM 2 '' VM 0 (1 '' e ''t/' ) (3.30) where VM 0 is the instant voltage value of VM when the digital input is switched from Din=0 to Din=256 and it is equal to: VM 0 = VC M + (VREF P '' VC M ) RP T,V CM 8 RP T,V CM 8 + RP T,V REF P + RT G,BP (3.31) Once the voltage signal VM (t) is settled, it reaches the final value due to the

voltage divider given by the capacitors. Therefore, the difference between

the final and initial voltage is equal to: ''V = VCM + VREF P '' VCM 2 '' VM 0 (3.32) While the time constant of the RC network is calculated as follows: ' = ( RP T,V CM 8 + RP T,V REF P + RT G,BP ) ' 8C (3.33) The settling time is then obtained by considering the time needed by the

output voltage to reach the final value within an error of 0.5LSBs''e , i.e.: VM (tsett) = = 0.5LSBs''e (3.34) 33 From Equation (3.30), the settling time is found as follows: tsett = ''' ln ''V (3.35) Considering minimum-size switches, the settling time tsett,calc estimated

from (3.35) for the worst case of DIN is 12 ns. The ADC presented in

this work reserves approximately 60 ns for the DAC settling time and the

preamplification. In order to relax the requirements on both speed of the

preamplifier and output resistance of the circuit providing the reference volt-

ages, a DAC settling time less than 5 ns is aimed. This can be easily achieved

by increasing the size of the switches in order to reduce their on-resistance,

calculating again the settling time and checking if it is short enough. In this

work the following dimensions have been used: W L P T,VREF N = 6 1 W L P T,VREF P = 18 1 W L T G,BP,N = 6 1 W L T G,BP,P = 18 1 W L P T,VCM = 4 1 where P TV REF N and P TVREF P are the pass-transistors providing VREF N and VREF P respectively, P TV CM is the pass-transistor passing VC M and T GBP,N and T GBP,P the NMOS and the PMOS transistors composing the transmis-

sion gate T GBP . Considering VREF P as reference voltage, the settling time

tsett,calc calculated using Equation (3.35) is 4.10 ns, while the Cadence simu-

lation of the circuit returns tsett,sim = 5.17 ns. Some values calculated using

this method are reported in Table 3.4 and compared with the results given

by the simulation using different switches sizes and both reference voltages.

As shown, it is possible to obtain a first rough estimation of the worst-case

settling time with this method. tsett,calc [ns] tsett,sim [ns] Minimum-size switches

VREF P = 2.65 V 12.00 13.91 VREF N = 0.65 V 11.87 13.15 Chosen switches

VREF P = 2.65 V 4.10 5.17 VREF N = 0.65 V 4.05 5.18 Table 3.4: Calculated and simulated settling time for DIN transiting from 0 to 256. 3.3.3 Other Switches So far, all the bottom-plate switches have been sized except the transmission-

gate T GSig which is directly connected to the input signal. This has been 34 sized to achieve a short settling time and good linearity, which will be further

discussed and analyzed in Section 3.4. Finally, for the top-plate NMOS

pass-transistor which resets the VL node, since low parasitic capacitance are

required on that node (Appendix 5.1), a minimum-size transistor has been

used. The LSB-subarray presents a relatively small equivalent capacitance,

hence even the minimum-size switch is sufficient to perform the reset. The

aspect ratios of the transistors composing these switches are summarized as

follows: W L T G,Sig,N = 10 1 W L T G,Sig,P = 30 1 W L P T,Res = 2 1 3.4 Comparator The comparator is an essential part in the SAR ADC to perform the binary

search algorithm. It has to discriminate voltage values as small as the differ-

ential LSBd''e. In addition, since it is usually the most power-hungry part

of the ADC, a power-efficient solution has to be found during the design. 3.4.1 Overview During the binary search phase, the comparator has to discriminate which

of the MSB sub-array top-plate nodes has higher voltage. This information

is passed then to the SAR logic control which can provide the correct digital

input value for the DAC. Ideally, only one latch is required to perform the

comparison. However, this is not feasible in reality because the latch usually

has a very high offset voltage and can introduce large kickback noise. In this

work, the comparator is composed of two preamplifiers and a latch, as shown

in Figure 3.20. The latch is then loaded with a digital logic that reduces the

metastability effect. Figure 3.20: Structure of the comparator stage. The proposed structure has been chosen for the following main reasons: ' Preamplification is required to overcome the offset voltage of the latch, especially for small input voltage values. ' Offset-cancellation techniques can easily be applied to the preamplifier stage, allowing a correct decision for the comparison. 35 ' The large kickback noise coming from the latch and affecting the ca- pacitive array is reduced due to the presence of the preamplifier. ' There is a minor kickback noise given by the preamplifiers. This can be reduced using two preamplifier stages while limiting the voltage

gain of the first one. 3.4.2 Latch In order to derive the design choices for the preamplifier, the latch stage is

first presented. The dynamic latch [16, 17] shown in Figure 3.21 has been

chosen to reduce the power consumption. When the control signal LatxS is

low, the reset phase is performed and the output nodes are pulled to VDD.

During the regeneration phase, LatxS is set to ''1'' and the circuit determines

which input signal is higher with the aid of the two cross-coupled inverters

M19, M23 and M20, M22. The decision is therefore taken on the rising edge

of the signal LatxS, as shown in Figure 3.22. Figure 3.21: Dynamic latch. Since this latch is dynamic, the power consumption is reduced. This is true

because the latch consumes power only when it is triggered. Otherwise,

during the reset phase, no static current is flowing through it. In addition,

it presents a high speed operation because the NMOS transistors M17-20

immediately enter the active region when the latch is triggered. This is

happening since, immediately after the reset phase, the source node voltages

of M19 and M20 are equal to VDD '' VT while the drain node voltage of M16

is VT below the latch input common mode voltage [18]. 36 Figure 3.22: Output response of the latch for a differential sinusoid input signal. Metastability is an important issue while designing comparators, hence the logic shown in Figure 3.23 has been chosen as load of the latch in order to

limit its influence. During the reset phase (LatxS signal low) the output logic

states Q and Q are kept at the same value, while during the regeneration

phase (LatxS signal high) they provide the output of the result given by the

latch. In case of a metastability error, both output nodes of the latch remain

close to VDD and the output logic maintains the previous values. Hence, the

error due to metastability is bounded in a range equal to ±1 LSBd''e. Figure 3.23: Load of the dynamic latch. Since the input capacitance of the OR gates is approximately 4 fF, the performance of the latch has been tested considering a generic output load

CL of 20 fF in order to have some margin. Considering the maximum transi-

tion of 3.3 V as reference value for the differential output, both regeneration

and reset time have been measured to be always less than 3 ns (Figure 3.24), 37 even for the voltage input as small as 1 LSBd''e. However, given that the

following OR gates can toggle with a smaller than 3.3 V differential output

voltage and the input signal of the latch is already amplified by the previous

stages, enough margin is reserved. Therefore, for the timing diagrams, the

interval between the rising edge of LatxS and a valid output logic state of

Q is chosen to be equal to 3 ns. Figure 3.24: Output response of the latch during the regeneration phase.. The power consumption of the latch can be estimated considering the following formula where IAvg is the average current provided by the power

supply: PLatch,Sim '' VDDIAvg (3.36) Considering that both the regeneration and reset phase are performed ten

times over a 781 ns conversion time and 1''000 cycles are simulated, the esti-

mated power consumption of the latch PLatch,Sim is approximately 7.68 µW. The input-referred offset voltage of the latch, VOS,Latch, has been esti- mated using the test bench [19] shown in Figure 3.25. The common-mode

voltage VCM is applied to an input node of the latch while a ramp signal is

controlling the other one. The ramp signal starts with a value lower than

VCM and increases with 1 mV steps. The regeneration phase is therefore

performed for each voltage level given by the ramp signal. Ideally, the latch

starts toggling when the ramp signal is larger than VCM . In a real circuit,

the corresponding differential input voltage is equal to VOS,Latch instead of

zero, as shown in Figure 3.25. The value of the input-referred offset voltage 38 of the latch is therefore estimated by carrying out a 1''000-runs Monte Carlo

simulation and measuring the differential input voltage. The results are the

following: ' µ(VOS,Latch) = 122 µV ' '(VOS,Latch) = 13.294 mV Figure 3.25: Test bench for the input-referred offset voltage estimation of the latch. Since the standard deviation of VOS,Latch is much larger than its mean value,

an estimation of the input-referred offset voltage value is obtained as follows: VOS,Latch '' 3'(VOS,Latch) = 39.883 mV (3.37) The offset value VOS,Latch of 40 mV will be considered in the forthcoming

calculations. Note, from the above estimation, the preamplifier stage is essential since the smallest differential input to be discriminated by the

comparator should be less than 1 LSBd''e. 3.4.3 Preamplifier Requirements The preamplifier stage is mainly added to suppress the effect of the large

kickback noise and offset voltage from the latch. It is a critical part in this

design, and the following specifications have to be met: ' The preamplifier has to overcome the input-referred offset voltage VOS,Latch of the latch, which is approximately 40 mV. Since the mini-

mum differential input value to be discriminated by the ADC is LSBd''e,

a required voltage gain AV,OS of the preamplifier can be estimated as

follows: AV,OS = VOS,Latch LSBs''e = 40 mV 3.906 mV = 10.23 '' 21 dB (3.38) 39 A 9 dB of margin can be added and thus the minimum voltage gain

AV,min is equal to: AV,min = 21 dB + 9 dB = 30 dB = 32 (3.39) ' Considering 12 cycles for the SAR analog-to-digital conversion (Sec- tion 3.5) and 1.28 MS/s as sampling frequency, each cycle lasts 65 ns.

In addition, reserving approximately 10 ns for both the regeneration

phase of the latch and the settling time of the DAC, the preamplifica-

tion of the input signal has to be performed in a time interval tP reAmp

less than 55 ns. In other words, the minimum differential input value

LSBd''e has to be correctly amplified during tP reAmp. ' The power consumption of the entire ADC should be less than 1 mW, hence reserving half of this value to the preamplifier stage, the maxi-

mum power consumption for this part will be: PP reAmp,max = PADC,max 2 = 500 µW (3.40) ' High values for the input capacitance of the preamplifier result in a large gain error for the DAC (Appendix 5.1). Therefore, the gate-area

of the input transistors has to be minimized. Two-stage preamplifier and kickback noise The preamplifier chosen has two stages and its structure is shown in Fig-

ure 3.26. Since the required minimum gain is not particularly high for this type of structure, diode-connected PMOS transistors have been used as

loads for the first stage while the second stage employs a resistive common-

mode feedback (R-CMFB) circuit [12, 20] where both resistors R are 110 k'.

Therefore, no active common-mode feedback network is required, leading to

a low power consumption. Furthermore, the area occupied by the resistors

is small because the process used provides a high-ohmic resistor option. Since a small unit capacitor is used for the capacitor array, the preampli- fier stage can influence the charge redistribution in the capacitor array due

to its kickback noise. When the input signal is sampled on the top-plate

node (VM ) of the MSB sub-array, this value is immediately amplified by

the preamplifier. However, due to the presence of the gate-to-drain overlap

capacitance CGD1 of the input transistor, the larger variation of the output

voltage of the first preamplifier can affect the node VM through this capaci-

tive path (Figure 3.27). This effect is called kickback noise [21]. If there is a

positive voltage step of VM , the kickback noise effect will decrease this step

size like that in a negative feedback loop. Clearly, the kickback noise also

affects the reference voltages given by the DAC during the binary search. 40 Figure 3.26: Two-stage preamplifier. Figure 3.27: Kickback noise in the first stage of the preamplifier. The analysis with the linear small-signal model of the transistors shows

that the given error is proportional to the voltage gain of the preamplifier,

as expected. Hence, the input voltage values of the comparator should be always scaled by the same factor, avoiding any distortion on the signal.

However, since the range of the input voltage is relatively large (equal to 2 V

considering only one of the two branches), the first stage of the preamplifier

may saturate. In this case, the output response of the preamplifier is not

linear anymore and the kickback noise is causing a distortion on the input

signal and, hence, limiting the linearity of the ADC. For this reason, a two-stage structure has been chosen for the pream- plifier where the first stage has a low voltage gain, which helps to reduce

the error caused by the kickback noise. Note that this design choice allows 41 also the use of small input transistors, leading to a small input capacitance

from the preamplifier as well. The linearity of the sampled signal has been

evaluated with a FFT analysis. For this simulation, a differential sinusoidal

voltage signal has been applied to the input of the ADC with peak-to-peak

amplitude close to F Sd''e and a frequency equal to BWSig. This results in

an SNDR equal to 69.92 dB (ENOB=11.32). Since the value obtained is

larger than 62 dB (ENOB = 10), a sufficient linearity is achieved during the

sampling phase. However, it is preferable to have some margin on this value.

This is obtainable by reducing the effect of the kickback noise even more

with the the capacitive neutralization technique [21, 22]. Since the output

voltages are affecting the input nodes through the gate-drain overlap capac-

itances of the input transistors, it is possible to add two dummy transistors

that approximately present an input capacitance close to CGD1 as shown in

Figure 3.28. To achieve this requirement, the dummy transistors are sized

using the same channel length and half of the width of the input pair M1,

M2: W L Dummy = 1 2 W L 1 (3.41) Therefore, the kickback noise through these overlap capacitances is reduced

and the improvement on the sampling linearity can be checked again with

a FFT analysis that returns an increased SNDR of 81 dB (ENOB=13.21). Figure 3.28: First preamplifier stage with dummy transistors using the capacitive neutralization technique. 42 Offset Cancellation and Sampling The offset of the comparator, which is constant and signal-independent,

causes also an offset of the ADC. This problem can be avoided limiting

or cancelling the offset at the comparator stage. The most famous offset

cancellation techniques [12, 23] are summarized as follows: ' Input offset storage (IOS): two relatively large series capacitors are added to the input nodes of the comparator and the preamplifier is

placed in a unity-gain negative-feedback loop operation. The offset

of the circuit is therefore measured and stored across the capacitors.

The residual input-referred offset voltage after the cancellation is the

following: VOS,Residual = VOS,P reAmp 1 + AV + ''Q C + VOS,Latch AV (3.42) where C is the value of each series capacitor and ''Q the charge-

injection due to the mismatch of the loop switches. As a drawback, this

technique requires a high gain value AV and also a large capacitance

to limit the the charge-injection error. ' Output offset storage (OOS): the series capacitors are now added to the output nodes of the preamplifier and the input nodes of the pream-

plifier shorted together during the offset cancellation. The nodes of the

capacitors not connected to the preamplifier are also shorted together

and thus the amplified offset voltage is stored on the capacitors. The

residual offset is given by the following equation: VOS,Residual = ''Q AV C + VOS,Latch AV (3.43) Hence, the offset of the preamplifier is completely cancelled and the

value of the series capacitor can be chosen smaller than before. How-

ever, since the preamplifier is performing an open-loop amplification,

it should not saturate. For this reason, the voltage gain is usually

limited to be less than 10. ' Active offset cancellation: The main drawback of the previous offset cancellation techniques is that they introduce capacitors in the signal

path. A possible solution is to perform the offset cancellation using an

auxiliary amplifier. The introduced amplifier can sense and subtract

the offset of the stage in a negative feedback loop. Obviously, this

technique is adding a new active element to the circuit, increasing the

overall power consumption. 43 Figure 3.29: Closed-loop operation of the preamplifier performing the input offset storage. In order to achieve a low-power operation for the presented SAR ADC,

the active offset cancellation can be discarded. Also the OOS technique

is not a promising solution because it requires additional output series ca-

pacitors and limits the gain of the preamplifier. Hence, the IOS has been

chosen since the capacitor arrays can be used as input series capacitances

and there is no limitation on the voltage gain. In addition, the entire array

of capacitors present a large equivalent capacitance that reduce the residue

offset caused by the charge injection mismatch, as shown in Equation (3.42),

while providing a sufficient phase margin during the closed-loop operation

of the preamplifier. In order to better understand the offset cancellation technique chosen, the equivalent circuit of the preamplifier placed in the closed-loop operation

is shown in Figure 3.29 where the offset voltage VOS,P reAmp is added and each

capacitive array is replaced with a series capacitor, respectively. Defining

Vin,d and Vout,d as the differential input and output voltage of the entire

preamplifier, the system of equations to be solved is the following: Vout,d = Vin,d Vout,d = (Vin,d + VOS,P reAmp)(''AV ) (3.44) where the DC gain of the preamplifier is equal to ''AV (unity-gain negative-

feedback). Solving the above equations, the result is the following: Vout,d = VOS,P reAmp ''AV 1 + AV (3.45) Referring the value obtained back to the input: Vin,diff = Vout,diff AV = '' VOS,P reAmp 1 + AV (3.46) That is the residual offset voltage of the preamplifier mentioned in Equa-

tion (3.42). At this point, it is possible to have an overview of the whole analog part of the SAR ADC and better understand how both sampling and offset 44 cancellation are performed. The simplified equivalent circuit of the previ-

ous designed circuits is shown in Figure 3.30 and the corresponding timing

diagram is represented in Figure 3.31. Figure 3.30: Simplified equivalent circuit of the analog part of the ADC. In Figure 3.30 the preamplifier stages are represented as ''PreA 1-2''. Ini-

tially, the input signal is applied to the bottom-plate nodes of the capacitive

array, the loop for the offset cancellation is closed and the output nodes

of each preamplifier are shorted together using switches. In this way, each

stage of the preamplifier is reset in a short period of time. After turning

off the ShortOutxS control signal, the loop can effectively perform the off-

set cancellation. Once the loop is open, also the path passing the input

signal can be disconnected and the common-mode voltage is connected to

the bottom-plate of each capacitor in the arrays. In order to correctly per-

form the bottom-plate sampling, the loop switches have to be open before

the switches connected to the input signal, whose charge injection is signal-

dependent. Therefore, any distortion effect is avoided on the sampled signal

at the input nodes of the comparator. Figure 3.31: Sampling timing diagram example. 45 Using the resistive common-mode feedback for the second stage, the top-

plate nodes of the MSB capacitor arrays are correctly reset during the offset

cancellation phase by the closed-loop operation, without the need of other

switches. The reset voltage value VRES for these nodes is approximately

1.70 V while the top-plate nodes of the LSB sub-array are reset to VCM

using two minimum-sized switches. After the signal has been sampled on

the input nodes of the preamplifier, the circuit can start the binary search

algorithm. Design, Analysis and Simulation The optimization of the preamplifier stage requires a thorough study of the

most relevant parameters in order to meet all the requirements. An analyti-

cal analysis has been first conducted and the performances are checked with

Cadence simulations. Considering first the power-speed trade-off, a tail current IT ail of 10 µA is reserved for each stage. The power consumption of the preamplifier is

therefore estimated as follows: PP reAmp '' 2VDDIT ail = 66 µW (3.47) Considering also the bias current, an overall power consumption of 75 µW

can be expected, which is less than the value reserved during the definition

of the requirements. The differential voltage gain AV of the preamplifier is defined as the product of the differential voltage gains of the first and second stage, AV 1

and AV 2 respectively: AV = AV 1AV 2 (3.48) where the differential gain of each preamplifier stage is approximately the

following: AV 1 = gm1 gm3 + gds1 '' gm1

gm3 (3.49) AV 2 = gm7 gds9 + 1 R + gds7 '' gm7R (3.50) where gm is the transconductance and gds the output conductance of the

transistors. The input transistors of both stages are operated in moderate

inversion to improve the values of the respective transconductances while all

the other transistors are operated in strong inversion. Since the input capacitance of the latch is approximately 4 fF, the circuit has been simulated in Cadence considering a generic capacitive output load

CL of 20 fF to have some margin. The results obtained are summarized in

Table 3.5 while the magnitude and phase diagrams of the open-loop transfer

function is shown in Figure 3.32. 46 Parameter Value AV 30.57 dB f''3 dB 33.54 MHz GBW P 1.13 GHz Power 72.60 µW Table 3.5: Preamplifier specifications. Figure 3.32: Magnitude and phase diagrams of the open-loop preamplifier transfer function. The speed of the preamplifier is another important requirement to be considered during the design. Considering that a bit decision has to be taken

approximately every 65 ns, the input signal should be correctly preamplified

in a time interval tP reAmp less than 55 ns. Applying a step input voltage

equal to LSBd''e, which is the minimum input value to be discriminated,

the differential output voltage reaches 129.4 mV after only 20 ns. Hence, the

input signal is sufficiently amplified in a short time interval since the output

reaches a value larger than the input-referred offset voltage of the latch.

Obviously, higher input values will achieve the requirements even faster. The

step responses of the differential outputs for both the preamplifier stages are

shown in Figure 3.33. When the noise is considered, the first stage of the preamplifier is an- alyzed since it is the major contributor. Both thermal and flicker (1/f ) 47 Figure 3.33: Step responses of the preamplifier stages for a LSBd''e differential

input. The blue trace represents the differential output voltage of the first stage, while the red trace shows the differential output voltage of the second stage. input-referred voltage noises can be estimated respectively as follows: e2 T hermal,in = 8kBT γ gm1 1 + gm3

gm1 (3.51) e2 F licker,in = 2K (1/f ) n CoxW1L1 1 f + 2K (1/f ) p CoxW3L3 1 f gm3 gm1 2 (3.52) where kB is the Boltzmann constant, T the temperature expressed in Kelvin,

K(1/f) a constant that depends on the technology, f the frequency, and γ a

coefficient which is around 2

3 for long channel devices and can be larger for deep sub-micron CMOS technologies. In order to evaluate the performance

of the circuit, the noise of the entire preamplifier can be integrated over

its frequency bandwidth and referred back to the input. In this way, it

is possible to compare it with the 0.5LSBd''e reference value. The noise

bandwidth is the following: BWNoise = ' 2 f''3 dB = 52.68 M Hz (3.53) where f''3 dB is the bandwidth of the preamplifier stage. In order to have

some margin, a noise bandwidth BWNoise equal to 1 GHz has been consid-

ered during the simulation. The integrated input-referred RMS value of the

noise of the stage is: ['Noise,in] 1 GHz

1 Hz = ['Noise,out] 1 GHz

1 Hz AV = 138.33 µVRMS (3.54) 48 where ['Noise,out] 1 GHz

1 Hz is the RMS value of the noise at the output nodes of the stage integrated on the 1 GHz bandwidth. Therefore, it is possible

to estimate the input-referred noise and compare it with the 0.5LSBd''e

reference value as follows: VNoise,P reAmp '' 3 ['Noise,in] 1 GHz

1 Hz = 415.00 µV 0.5LSBd''e (3.55) Since VNoise,P reAmp is much less than the 0.5LSBd''e reference value, the

stage has a good noise performance. Statistic offset voltage can affect the performance of the preamplifier and hence of the entire ADC. The input-referred offset voltage of the first stage

can be estimated as follows: VOS,P reAmp = VOS,1 + VOS,3 gm3

gm1 (3.56) where VOS,1 and VOS,3 are the variables representing the equivalent statistic

offset voltage values of M1, M2 and M3, M4 respectively. The variance of

these variables can be found as follows: ' 2(V OS ) = ' 2(''V T ) + ' 2 ''β β ID gm 2 (3.57) where ''VT and ''β represent the threshold voltage and current factor mis-

match respectively. Using Pelgrom coefficients [24, 25]: '(''VT ) = AV T '' W L (3.58) ' ''β β = Aβ '' W L (3.59) From a 1''000-runs Monte Carlo simulation, the input-referred offset voltage

VOS,P reAmp is estimated as follows: VOS,P reAmp '' 3'(''VOUT ) AV = 20.66 mV (3.60) where ''VOUT is the difference between the DC values of VopA and VonA.

Since the offset voltage of the preamplifier stage is larger than LSBd''e, an

offset cancellation technique is required. The chosen input offset storage

technique returns the following residual input-referred offset voltage after

the cancellation: VOS,Residual = VOS,P reAmp 1 + AV = 594.40 µV (3.61) Again, this residual voltage value can be compared to the 0.5LSBd''e reference value and note that the smallest differential input signal can be

therefore estimated after the cancellation. 49 The offset cancellation is performed in an unity-gain negative-feedback loop configuration during the sampling phase, hence, the stability of the

stage has to be checked. The preamplifier reaches a phase margin P M of

78.40' during the closed-loop mode, providing a safe margin for the stability.

Due to the large equivalent capacitance at the input nodes of the comparator

provided by the capacitive array, the first dominant pole of the loop gain

transfer function is shifted towards low frequencies, improving the stability

of the system. The magnitude and phase diagram of the loop gain are shown

in Figure 3.34. Figure 3.34: Magnitude and phase diagrams of the loop gain transfer function. 3.5 SAR Control Logic A control logic is required to control both the S/H and the DAC, to fi-

nally perform the binary search algorithm. Once the latch has made its

decision, the result is stored in the register and the DAC digital input is up-

dated according to the decision. During this closed-loop operation, timing

requirements have to be met and, again, low-power solutions are preferred. 3.5.1 Timing Diagrams Since 16 ADCs are going to be implemented in the chip, a sampling fre-

quency fs of 1.28 MHz has been chosen during the elaboration of specifica-

tions in Section 2.2. Therefore, each ADC has a conversion time tconv equal 50 to: tconv = 1 fs '' 781 ns (3.62) One analog-to-digital conversion is carried out in 12 clock cycles as designed

in this work. While the first cycle is reserved to reset the output voltage of

the comparator stages, the second one is used to sample the input signal.

The remaining 10 cycles are required for the 10-bit conversion. Therefore,

for each cycle the following time interval tcycle is needed: tcycle = tconv 12 '' 65 ns (3.63) Hence, a master clock frequency fclk equal to 15.36 MHz is required. The

timing diagrams of the conversion are represented in Figure 3.35. All the

digital control signals are generated from the master clock signal ClkxC

and a second clock signal ClkdxC which is delayed by 3 ns with respect

to ClkxC. Note that the digital signal ClkdxC is mostly used to generate

the short pulses that trigger the latch and allows the circuit to perform the

bottom-plate sampling. Moreover, the digital signal ShortOutxS is high to

short the output nodes of each preamplifier, LoopxS is the control signal

that closes the loop, SelInxS becomes high when the input signal is applied

to the capacitive array, DIN is the digital input of the DAC and LatxS is

the control signal for the latch. The signal DigOutxS represents the first

9 bits of the output digital value while SignxS is the MSB (sign bit). It is

important to observe that DIN is equal to DigOutxS when its first 8 bits

are determined (from cycle #4 to cycle #12) but it is reset at the beginning

of the new conversion. The value of the last bit of DigOutxS is instead

assigned at this time, therefore the 10-bit output digital value is ready to be

saved in a register during cycle #2, when the end-of-conversion signal EocxS

is high. During the first cycle the preamplifier stages are reset, as indicated

from the digital control signal ShortOutxS that is set to ''1''. The input

signal is effectively sampled on the bottom-plate nodes of the capacitors in

the second cycle since LoopxS and SelInxS are both high. At this time the

preamplifier is operating in closed-loop, hence also the offset cancellation is

performed. LoopxS is set to ''0'' before the ending of the cycle in order to

realize the bottom-plate sampling. At the third cycle, all the bottom-plate

nodes of the capacitors are connected to the common voltage (DIN equal

to ''0'') and the sampled charge is redistributed on the input nodes of the

comparator. The first comparison can be therefore executed and the MSB

is determined at the beginning of the fourth cycle when the latch is triggered.

The timing diagrams of the first three cycles are shown in Figure 3.36.

At the beginning of the cycle #4 the reference voltages (VREF P and VREF N )

are assigned to the corresponding capacitor arrays depending on the result of

the last comparison and the DAC input signal is set to its half-range value.

Hence, the cycles from #4 to #12 are used to determine the remaining 9 51 Figure 3.35: Timing diagrams of the SAR control logic. 52 Figure 3.36: Timing diagrams for the first three cycles of a conversion. bits with the binary search algorithm. In particular, at the beginning of

each cycle, each DAC provides a new voltage value based on the previous

bit-decision, while the preamplifier amplifies the difference between its input

nodes and the latch makes a decision once it is triggered (when the LatxS

signal goes high). On the new cycle, the digital input DIN of the DAC will

be eventually updated depending on the previous comparison result and

a new voltage value will be provided. A part from the fourth cycle, the

remaining cycles are clearly all equal, as shown in Figure 3.37 where cycles

#4, #5 and #6 are illustrated. 3.5.2 SAR Control Logic Implementation The digital part of this ADC has been implemented as a successive approx-

imation register (SAR) whose simplified structure is shown in Figure 3.38.

Two rows of flip-flops are used to generate the digital input signal DIN for

the DAC: the first row is a shift register that shifts a logical ''1'' while each

flip-flop of the second row is first set to logical ''1'' and then is eventually reset 53 Figure 3.37: Timing diagrams of the cycles used to determine the last 9 bits of the digital output. to logical ''0'', depending on the result of the comparison given by the signal

CompxS. The solution presented is quite popular in SAR ADCs [26, 27]

and it based on the design proposed in [28]. Considering the entire chip that

will host the 16 SAR ADCs, the shift register can be shared among them in

order to reduce both overall area and power consumption. 3.5.3 Delay Elements A second clock signal delayed by 3 ns is required by the SAR control logic

and it is generated using a chain of inverters accurately sized. In order

to increase the delay, as shown in Figure 3.39, the chain consists of two

inverters using transistors with larger length L equal to 4.2 µm and two

minimum-sized inverters added both to the input and the output of the

chain. This design choice allows to have larger output resistance for the

sized inverters, increasing the time delay while minimizing the capacitive

load for the driving circuit. The first two minimum-sized inverters are used

to drive the structure while the last two one allow the circuit to achieve 54 Figure 3.38: Successive approximation register for binary search. shorter rise and fall time. A generic output load CL of 10 fF has been used

to evaluate the time delay tD, the 10%-to-90% rise time tR, the 90%-to-10%

fall time tF and the dynamic power consumption. Simulating the circuit,

the values obtained are the following: a delay time tD of 3.446 ns is achived,

rise time and fall time are respectively equal to 248 ps and 186 ps, while the

power consumption is equal to 21.043 µW. Nevertheless, this block can be

shared among all the ADCs present on chip. Figure 3.39: Chain of inverters to generate the delayed clock signal. 3.6 Layout The layout of the entire SAR ADC is shown in Figure 3.40. The dimen-

sions of this block are 395 ' 391 µm2, leading to an overall area AADC of

1540445 µm2. The floorplan is illustrated in Figure 3.41 where the different

parts have been highlighted. These parts are the two capacitive arrays and

their relative switches, the comparator and the digital part required for each

ADC. As expected, the capacitive array occupies the largest amount of area

among all blocks. The layout has been conducted while in a way to make 55 Figure 3.40: Floorplan of the SAR ADC. a compact structure. However, the analog part has been placed at a safety

distance of approximately 100 µm from the digital circuits to reduce the

coupling noise coming through the substrate [29].

Some of the digital part of the ADC is shared among all the ADCs on chip

(Section 3.5) and its layout is shown in Figure 3.42. The dimensions of this

part are 142 ' 87 µm2, for an area ADigShared of 12 0354 µm2. Considering again the implementation of all the SAR ADCs on chip, at this point it is possible to estimate the overall required area. One possible

floorplan for the MEA chip is to place 1''024 read-out channels on two sides

of the chip, i. e., 512 channels are reserved for each side. Thus, the 16 SAR

ADCs can also be split in two groups while adding the digital shared logic

to each of them. The floorplan of the ADCs implemented on chip is shown

in Figure 3.43. Hence, the overall area required on chip can be estimated as

follows: AADC,Chip = 16AADC + 2ADigShared '' 2.50mm 2 (3.64) 56 Figure 3.41: Analog and digital blocks composing the SAR ADC. Figure 3.42: Layout of the shared digital logic among all the ADCs on chip. Figure 3.43: Floorplan of the ADCs integrated on the MEA chip. 57 Chapter 4 Simulations and Conclusions 4.1 Simulation Results In order to evaluate the performance of the designed circuit, the charac-

terization of the SAR ADC has to be conducted running different post-

layout simulations. First of all, an example of analog-to-digital conversion

is presented in Figure 4.1 where the reported voltage signals are measured

at the input nodes of the preamplifier (VipA and VinA). Both the sign-bit

SignxS and the remaining 9 bits DigOutxS composing the digital output

are shown as well. The conversion has been done for a constant analog input

value whose amplitude is equal to the differential full-scale F Sd''e. Hence,

the SAR ADC provides the highest value for the digital output. Note that

SignxS is equal to ''1'' if the differential input voltage is positive, while the

remaining 9 bits are given by DigOutxS. Differential and integral linearity errors (DNL and INL respectively) can be evaluated using the histogram test with a linear ramp input [4]. In this

kind of simulation consists a large number of digitized samples is collected

from the ADC for an input signal with known probability density function,

such as a linear ramp. From the simulation results, both DNL and INL

histogram plots can be derived and they are shown in Figures 4.2 and 4.3

respectively. Both DNL and INL errors are less than 0.5 LSBd''e for each

digital output. The resolution of the presented linearity analysis is equal to

0.05 LSBd''e. A 2''048-points FFT analysis is run to evaluate both the SNDR and SFDR of the converter. The sampling frequency fs is set to 1.28 MS/s

while the frequency of the input sinusoidal wave is close to 10 KHz which is

the bandwidth BWsig of the neural signals. The output of the FFT analysis

is a power spectral density graph and is shown in Figure 4.4. The SFDR

measured is 76.51 dB while the SNDR reaches 60.74 dB that leads to an

ENOB of 9.79. The power consumptions of both analog and digital parts of the ADC 58 Figure 4.1: Example of an analog-to-digital conversion performed by the SAR ADC. Figure 4.2: DNL histogram plot of the SAR ADC. are finally measured. Note, the digital control logic is divided into two parts:

one part is added to each converter (Digital) while the other one is shared

all the ADCs (Shared digital) present on chip, as explained in Section 3.6.

For this reason, in Table 4.1 the two different digital power consumptions

are distinguished.

For the MEA chip application, the overall power consumption of the ADCs

is therefore estimated as follows: PT ot = 16(PAnalog + PDigital) + 2PSharedDigital = 2.25 mW (4.1) Altough the proposed data converter is not supposed to be general-purpose, 59 Figure 4.3: INL histogram plot of the SAR ADC. Figure 4.4: 2''048-points FFT output of the SAR ADC. Part Power [µW ] Analog 95.24 Digital 31.88 Shared digital 105.80 Table 4.1: Summary of the ADC power consumption. its power efficiency can be estimated with the following figure of merit: F oM = PADC 2ENOBfS (4.2) 60 where PADC is the total power consumption of one ADC and, for the case

presented, is estimated as: PADC = PT ot 16 = 140.63 µW (4.3) That leads to a FoM of 125 fJ/conv-step. Note that this figure of merit is

calculated without considering the power consumptions of the multiplexers

and buffers required by the system. Table 4.2 summarizes and compare both the requirements and the es- timated specifications for the designed SAR ADC. In addition, the perfor-

mance of the proposed data-conversion system that can be integrated on

the MEA chip is shown in Table 4.3. These results are compared with the

specifications of the single-slope ADCs currently integrated on the latest

version of the MEA chip. Parameter Requirements Estimated values Resolution 10 bits Sampling Rate 1.28 MS/s Supply Voltage 3.3 V Full Scale Range 2.0 Vpp (differential) DNL < 0.5 LSB + 0.35 / - 0.35 LSB INL < 1 LSB + 0.35 / - 0.35 LSB ENOB 9 bits 9.79 bits SNDR ' 56 dB 60.74 dB SFDR - 76.51 dB Area ' 1 mm2 0.157 mm2 Power Consumption ' 1 mW 140.7 µW Technology 0.35 µm CMOS Table 4.2: Requirements and estimated performance of a single SAR ADC. ADC Single-Slope SAR Resolution 10 bits ENOB 9.7 bits 9.79 bits Area 7.04 mm2 2.50 mm2 Analog Power Consumption 6.19 mW 1.53 mW Table 4.3: Specifications of the single-slope data-conversion system currently im- plemented on chip, compared to the performance of the SAR ADCs. 61 4.2 Conclusions The presence of integrated analog-to-digital converters on chip is an essential

requirement for allowing a good signal transmission between the chip and

the external devices. After comparing the most relevant topologies for data

converters, the SAR ADC has been chosen since it is a promising solution

that could meet the required specifications by multiplexing the read-out

channels on the MEA chip. Both low power consumption and low complexity

of the circuit are relevant advantages of the chosen ADC and key aspects to

succeed in the design. Switched-capacitor arrays are used to implement both the S/H and DAC while minimizing the value of the unit capacitor. The arrays are split in two

parts to reduce the overall equivalent capacitance which is equal to 6.05 pF

for a unit capacitor of only 64.36 fF. The capacitance provided by this part

can be used to store the offset voltage of the preamplifier and cancel its

effect on the ADC performance. In fact, the residual input-referred offset

voltage of the amplifier is 594.40 µV after the cancellation, that is largely

less than the LSB value. While considering the timing requirements, the

sizes of the switches are optimized to reduce their area. In this work, the

switches occupy only 1.72 % of the total area of the ADC. A low-power

two-stage preamplifier is designed to improve the efficiency of the compar-

ison and drive the input nodes of the latch. In fact, the preamplifier can

overcome the large offset voltage of the latch, that is estimated to be 40 mV

in the worst case. Moreover, the effect of the kickback noise caused by

the preamplifier is reduced by using the capacitive neutralization technique,

leading to ENOB of 13.21 for the linearity quality of the sampling. The dig-

ital part is implemented adopting a successive approximation register whose

shift register is shared among all the ADCs present on chip, therefore saving

the 67.23 % of the digital power consumption. The ADC occupies an area of 0.157 mm2 and presents an overall power consumption of 140.63 µW for a sampling frequency of 1.28 MS/s. From

the post-layout simulation results, both DNL and INL errors are bounded

in a 0.35 LSB range. Concerning the linearity of the ADC, an ENOB of

9.79 is obtained. The power efficiency is estimated with the FoM defined

in (4.2), that is equal to 125 fJ/conv-step. Finally, comparing this simulation

results with the specifications of the single-slope ADCs currently integrated

on the latest version of the MEA chip, the proposed data-conversion system

presents an improvement of 64.49 % in terms of area reduction and its analog

power consumption is 4 times less. In conclusion, the presented SAR ADC has proved to be a promising solution for low-power applications. All the preliminary requirements have

been met and a good performance achieved. The specifications of the data-

conversion system have been compared with the ADCs currently imple-

mented on the MEA chip and a possible improvement of its performances 62 has been presented. The designed circuit is therefore ready to be integrated

on chip for a final characterization based on real measurements. 63 Chapter 5 Appendix 5.1 Effects of the parasitic capacitances in the DAC The equivalent circuit of the switched-capacitor DAC is shown in Figure 5.1

where m and p are the sums of the unit capacitors connected in parallel

to the reference voltage in the LSB sub-array and MSB sub-array respec-

tively (Section 3.2). In addition, the parasitic capacitances affecting both

VL and VM nodes, Cp1 and Cp2 respectively, are added to the equivalent

circuit. While Cp1 is the bottom-plate parasitic capacitance of the series

capacitor C, Cp2 represents the gate capacitance of the input transistors of

the comparator. Figure 5.1: Switched-capacitor DAC equivalent circuit. Considering first the ideal case where no parasitic capacitances are present in the circuit (Cp1 = 0 and Cp2 = 0) and assuming that all the capacitors

are discharged before applying the digital input signal, the equations given 64 by the charge conservation principle are the following: 0 = mC(VL '' VREF P ) + (15 '' m)C(VL '' VCM ) + C(VL '' VM ) 0 = pC(VM '' VREF P ) + (31 '' p)C(VM '' VCM ) + C(VM '' VL) Solving the previous system of equations, the output voltage VM of the DAC

is: VM = VCM + (VREF P '' VCM ) m + 16p 511 (5.1) If the parasitic capacitances are taken into account, the previous system of

equations is modified as follows: Cp1(VCM '' VDD) = mC(VL '' VREF P ) + (15 '' m)C(VL '' VCM ) + +C(VL '' VM ) + Cp1(VL '' VDD) Cp2(VCM '' VDD) = pC(VM '' VREF P ) + (31 '' p)C(VM '' VCM ) + +C(VM '' VL) + Cp2(VM '' VDD) that results in the following output voltage VM for the DAC: VM = VCM + (VREF P '' VCM ) m + 16p + pCp1 511 + 32Cp1 + 16Cp2 + Cp1Cp2 (5.2) It is therefore possible to study the influence of the parasitic capacitances

on the DAC by comparing (5.2) with (5.1). In fact, while both parasitic

capacitances are introducing a gain error, only Cp1 is causing a distortion

on the DAC, hence limiting its linearity. Finally, note that, since the gate

capacitance Cp2 is usually larger than Cp1, the gain error is mostly given by

the gate capacitance of the comparator''s input transistors. 5.2 Standard deviation estimation of the DAC out-

put voltage Considering a simple 3-bit binary-weighted switched-capacitor DAC, the

analytical estimation of the standard deviation for its output voltage is pre-

sented in this section. The capacitive array and the equivalent circuit are

shown in Figure 5.2. The output voltage of the 3-bit DAC for the half-range

digital input code (DIN = 4 = 100) presents the worst case in terms of

mismatch among the capacitors [11], hence the constriction on the standard

deviation of this voltage should satisfy the following condition: 3'(VM,D IN =4) ' 0.5LS B (5.3) 65 Figure 5.2: 3-bit switched-capacitor DAC and its equivalent circuit. Defining Ceq=C+C+2C, the output voltage value for the half-range digital

input code is the following: VM,D IN =4 = VC M + (VREF P '' VC M ) 4C 4C + Ceq = 2.15 V (5.4) Considering the capacitances as independent random variables, the mean

value of VM,D IN =4 is: µ(VM,D IN =4) = 2.15 V (5.5) On the other hand, the calculation of the standard deviation '(VM,D IN =4) requires more steps. Calculating first both the mean value and the variance

of the equivalent capacitance Ceq: µ(Ceq) = µ(C) + µ(C) + µ(2C) = 4µ(C) ' 2(C eq ) = ' 2(C) + '2(C) + '2(2C) = 4'2(C) Adding the value of the MSB capacitance 4C: µ(4C + Ceq) = µ(4C) + µ(Ceq) = 8µ(C) ' 2(4C + C eq ) = ' 2(4C) + '2(C eq ) = 8' 2(C) Hence, the variance of the capacitive-divider ratio is: ' 2 4C 4C + Ceq = µ(4C) µ(4C + Ceq) 2 '2(4C) µ2(4C) + '2(4C + Ceq)

µ2(4C + Ceq) 2 = 3'2(C) 32µ2(C) The variance of VM,D IN =4 is therefore found as follows: ' 2(V M,DIN =4) = ' 2 VCM + (VREF P '' VCM ) 4C 4C + Ceq = = (VREF P '' VCM ) 2 3' 2(C) 32µ2(C) 66 Writing µ(C) as µC and '(C) as 'C, the standard deviation of VM,D IN =4 is the following: '(VM,D IN =4) = (VREF P '' VC M ) '' 6'C 8µC (5.6) Since both µC and 'C depend on the area of the unit capacitor, by substi-

tuting the parametric expressions in (5.3), one can determine the minimum

unit capacitor area that satisfies the condition. 67 Bibliography [1] A. Hierlemann, U. Frey, S. Hafizovic et al., ''Growing cells atop micro- electronic chips: Interfacing electrogenic cells in vitro with CMOS-based

microelectrode arrays,' Proc. IEEE, vol.99, pp.252-284, Feb. 2011. [2] U. Frey, J. Sedivy, F. Heer et al., ''Switch-matrix-based high-density mi- croelectrode array in CMOS technology,' IEEE J. Solid-State Circuits,

vol.45, pp.467-482, Feb. 2010. [3] R. R. Harrison, ''The Design of Integrated Circuits to Observe Brain Activity,' Proc. IEEE, vol.96, no.7, pp.1203-1216, Jul. 2008. [4] W. Kester, ''The Data Conversion Handbook,' Analog Devices, Inc., 2005. [5] J. L. McCreary and P. R. Gray, ''All-MOS charge redistribution analog- to-digital conversion techniques-Part I,' IEEE J. Solid-State Circuits,

vol.SC-10, no.6, pp.371-379, Dec. 1975. [6] R. J. Baker, ''CMOS Circuit Design, Layout and Simulation,' Wiley- IEEE Press, 2010. [7] B. Razavi, ''Data Conversion System Design,' IEEE Press, 1995. [8] C. Liu, S. Chang, G. Huang and Y. Lin, ''A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,' IEEE J. Solid-State

Circuits, vol.45, no.4, pp.731-740, Apr. 2010. [9] L. Cong, ''Pseudo C-2C ladder-based data converter technique,' Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transac-

tions on, vol.48, no.10, pp.927-929, Oct. 2001. [10] S. Haenzsche, S. Henker and R. Schuffny, ''Modelling of capacitor mis- match and non-linearity effects ini charge redistribution SAR ADCs,'

Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Pro-

ceedings of the 17th International Conference, pp.300-305, 24-26 Jun.

2010. 68 [11] Z. Lin, H. Yang, L. Zhong, J. Sun and S. Xia, ''Modeling of capacitor array mismatch effect in embedded CMOS CR SAR ADC,' ASIC, 2005.

ASICON 2005. 6th International Conference On, vol.2, no., pp.982-986,

24-27 Oct. 2005. [12] B. Razavi, ''Design of Analog CMOS Integrated Circuits,' McGraw- Hill, 2001. [13] A. Agnes, E. Bonizzoni, P. Malcovati and F. Maloberti, ''A 9.4 EnoB, 1V, 3.8uW, 100kS/s SAR-ADC with Time-Domain Comparator,' IEEE

International Solid-State Circuits Conference (ISSCC), 2008. [14] N. H. E. Weste and D. M. Harris, ''CMOS VLSI Design: A Circuits and Systems Perspective,' Addison-Wesley, Fourth Edition, 2011. [15] A. Hastings, ''The Art of Analog Layout,' Prentice Hall, Second Edi- tion, 2006. [16] T. Kobayashi, K. Nogami, T. Shirotori and Y. Fujimoto, ''A current- controlled latch sense amplifier and a static power-saving input buffer

for low-power architecture,' Solid-State Circuits, IEEE Journal, vol.28,

no.4, pp.523-527, Apr. 1993. [17] S. Cho, C. Lee, J. Kwon and S. Ryu, ''A 550-µW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction,' Solid-

State Circuits, IEEE Journal, vol.46, no.8, pp.1881-1892, Apr. 2011. [18] K. Y. Kim, ''A 10-bit, 100 MS/s Analog-to-Digital Converter in 1- µm CMOS,' PhD Thesis, Integrated Circuits & Systems Laboratory

Electrical Engineering Department, University of California, Jun. 2006. [19] A. Graupner, ''A Methodology for the Offset Simulation of Com- parators,' The Designer''s Guide Community, www.designers-guide.org,

2006. [20] B. Song, M. Choe, P. Rakers and S. Gillig, ''A 1 V 6 b 50 MHz current- interpolating CMOS ADC,' VLSI Circuits, 1999. Digest of Technical

Papers. 1999 Symposium, pp.79-80, 1999. [21] P. M. Figueiredo and J. C. Vital, ''Low kickback noise techniques for CMOS latched comparators,' Circuits and Systems, 2004. ISCAS ''04.

Proceedings of the 2004 International Symposium, vol.1, pp.I- 537-40

Vol.1, May 2004. [22] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, ''Analysis and Design of Analog Integrated Circuits,' John Wiley & Sons, INC., Fourth

Edition, 2001. 69 [23] B. Razavi and B. A. Wooley, ''Design techniques for high-speed, high- resolution comparators,' Solid-State Circuits, IEEE Journal, vol.27,

no.12, pp.1916-1926, Dec. 1992. [24] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, ''Match- ing properties of MOS transistors,' Solid-State Circuits, IEEE Journal,

vol.24, no.5, pp. 1433- 1439, Oct. 1989. [25] P. R. Kinget, ''Device mismatch and tradeoffs in the design of analog circuits,' Solid-State Circuits, IEEE Journal, vol.40, no.6, pp. 1212-

1224, Jun. 2005. [26] M. D. Scott, B. E. Bose and K. S. J. Pister, ''An ultralow-energy ADC for Smart Dust,' Solid-State Circuits, IEEE Journal, vol.38, no.7, pp.

1123- 1129, Jul. 2003. [27] Y. Zhu, C. Chan, U. Chio, S. Sin, S. Sin, S. U, R. P. Martins and F. Maloberti, ''A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm

CMOS,' Solid-State Circuits, IEEE Journal, vol.45, no.6, pp.1111-1121,

Jun. 2010. [28] T. O. Anderson, ''Optimum Control Logic for Successive Approxima- tion Analog-to-Digital Converters,' Comput. Design, vol.11, no.7, pp.81-

86, Jul. 1972. [29] D. K. Su, M. J. Loinaz, S. Masui and B. A. Wooley, ''Experimental results and modeling techniques for substrate noise in mixed-signal in-

tegrated circuits,' Solid-State Circuits, vol.28, no.4, pp.420-430, Apr.

1993. 70

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